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| 型号： | MAX17482GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 43/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL IMVP-6.5 40TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
f ESR ≤ SW
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V SAG and V SOAR from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the V SAG and V SOAR equations
in the Transient Response section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
f
π
where:
Their relatively low capacitance value can cause output
overshoot when stepping from full-load to no-load con-
ditions, unless a small inductor value is used (high
switching frequency) to minimize the energy transferred
from inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and feedback-
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is not
enough voltage ramp in the output-voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
f ESR =
1
2 π R EFF C OUT
tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
η TOTAL V OUT ( V IN - η TOT A L V OUT )
I RMS = ?
and:
R EFF = R ESR + R DROOP + R PCB
where C OUT is the total output capacitance, R ESR is the
total equivalent series resistance, R DROOP is the volt-
age-positioning gain, and R PCB is the parasitic board
resistance between the output capacitors and sense
resistors.
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard application circuit, the ESR needed to support
a 30mV P-P ripple is 30mV/(40A x 0.3) = 2.5m Ω . Four
330μF/2.5V Panasonic SP (type SX) capacitors in paral-
lel provide 1.5m Ω (max) ESR. With a 2m Ω droop and
0.5m Ω PCB resistance, the typical combined ESR
results in a zero at 30kHz.
Ceramic capacitors have a high-ESR zero frequency,
but applications with significant voltage positioning can
take advantage of their size and low ESR. Do not put
high-value ceramic capacitors directly across the out-
put without verifying that the circuit contains enough
voltage positioning and series PCB resistance to
ensure stability. When only using ceramic output
capacitors, output overshoot (V SOAR ) typically deter-
mines the minimum output capacitance requirement.
observe the output-voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I RMS ) imposed by the switching currents.
The multiphase Quick-PWM controllers operate out-of-
phase while the Quick-PWM slave controllers provide
selectable out-of-phase or in-phase on-time triggering.
Out-of-phase operation reduces the RMS input current
by dividing the input current between several stag-
gered stages. For duty cycles less than 100%/ η OUTPH
per phase, the I RMS requirements can be determined
by the following equation:
? I LOAD ?
?
? η TOTAL V IN ?
where η TOTAL is the total number of out-of-phase
switching regulators. The worst-case RMS current
requirement occurs when operating with V IN =
2 η TOTAL V OUT . At this point, the above equation simpli-
fies to I RMS = 0.5 x I LOAD / η TOTAL .
______________________________________________________________________________________
43
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