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参数资料
| 型号： | MAX17482GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 40/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL IMVP-6.5 40TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
V GS ( TH ) > V IN ? RSS ?
pulse-skipping operation (DPRSLPVR = high), the OVP
threshold is set to default.
When the OVP circuit detects an overvoltage fault, the
MAX17021/MAX17082 immediately force DL1 high and
pull DH1 and DH2 low. This action turns on the syn-
chronous-rectifier MOSFETs with 100% duty and, in
turn, rapidly discharges the output filter capacitor and
forces the output low. If the condition that caused the
overvoltage (such as a shorted high-side MOSFET) per-
sists, the battery fuse will blow. Toggle SHDN or cycle
the V CC power supply below 0.5V to clear the fault
latch and reactivate the controller.
Overvoltage protection can be disabled through the no-
fault test mode (see the No-Fault Test Mode section).
Output Undervoltage Protection (UVP)
If the MAX17021/MAX17082/MAX17482 output voltage is
400mV below the target voltage, the controller activates
the shutdown sequence and sets the fault latch. Once
the controller ramps down to zero, it forces DL1 and DL2
high, and pulls DH1 and DH2 low. Toggle SHDN or cycle
the V CC power supply below 0.5V to clear the fault latch
and reactivate the controller.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
Thermal-Fault Protection
The MAX17021/MAX17082/MAX17482 feature a ther-
mal-fault-protection circuit. When the junction tempera-
ture rises above +160°C, a thermal sensor sets the fault
latch and activates the soft-shutdown sequence. Once
the controller ramps down to zero, it forces DL1 and
DL2 high, and pulls DH1 and DH2 low. Toggle SHDN or
cycle the V CC power supply below 0.5V to clear the
fault latch and reactivate the controller after the junction
temperature cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched fault-protection features can complicate
the process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to deter-
mine what went wrong. Therefore, a no-fault test mode
is provided to disable the fault protection—overvoltage
protection, undervoltage protection, and thermal shut-
down. Additionally, the test mode clears the fault latch if
it has been set. The no-fault test mode is entered by
forcing 11V to 13V on SHDN .
MOSFET Gate Drivers
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V IN -
V OUT differential exists. The high-side gate drivers
(DH_) source and sink 2.2A, and the low-side gate dri-
vers (DL_) source 2.7A and sink 8A. This ensures
robust gate drive for high-current applications. The DH_
floating high-side MOSFET drivers are powered by
internal boost switch charge pumps at BST_, while the
DL_ synchronous-rectifier drivers are powered directly
by the 5V bias supply (V DD ).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; other-
wise, the sense circuitry in the MAX17021/MAX17082/
MAX17482 interprets the MOSFET gates as off while
charge actually remains. Use very short, wide traces
(50 mils to 100 mils wide if the MOSFET is 1in from the
driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.25 Ω (typ) on-resistance. This helps
prevent DL_ from being pulled up due to capacitive
coupling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX_) quickly
switches from ground to V IN . Applications with high
input voltages and long inductive driver traces might
require rising LX_ edges do not pull up the low-side
MOSFETs’ gate, causing shoot-through currents. The
capacitive coupling between LX_ and DL_ created by
the MOSFET’s gate-to-drain capacitance (C RSS ), gate-
to-source capacitance (C ISS - C RSS ), and additional
board parasitics should not exceed the following mini-
mum threshold:
? C ?
? C ISS ?
Typically, adding a 4700pF between DL_ and power
ground (C NL in Figure 11), close to the low-side
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
40
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