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| 型号： | MAX17482GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 45/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL IMVP-6.5 40TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel IMVP-6，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can over design the cir-
cuit to tolerate:
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (C CCI )
integrates the difference between the main and sec-
I LOAD = η TOTAL ? I VALLEY ( MAX ) +
?
?
Δ I INDUCTOR ?
?
2 ?
ondary current-sense voltages. The internal compensa-
tion resistor (R CCI = 200k Ω ) improves transient
response by increasing the phase margin. This allows
the dynamics of the current-balance loop to be opti-
= η TOTAL VALLEY ( MAX ) + ?
?
N × Q GATE
C BST _ =
R FB =
R SENSE m ( FB )
? I LOAD(MAX ) LIR ?
I
? 2 ?
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D L ) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current per phase dur-
ing the dead times. This diode is optional and can be
removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (C BST_ ) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1 μF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1μF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
200 mV
where N is the number of high-side MOSFETs used for
one regulator, and Q GATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V GS = 5V). Using the above equation, the required
boost capacitance would be:
mized. Excessively large capacitor values increase the
integration time constant, resulting in larger current dif-
ferences between the phases during transients.
Excessively small capacitor values allow the current
loop to respond cycle-by-cycle, but can result in small
DC current variations between the phases. For most
applications, a 470pF capacitor from CCI to the switch-
ing regulator’s output works well.
Connecting the compensation network to the output
(V OUT ) allows the controller to feed-forward the output-
voltage signal, especially during transients.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor ’s power-dissipation
requirements. The controller uses a transconductance
amplifier to set the transient and DC output-voltage
droop (Figure 3) as a function of the load. This adjusta-
bility allows flexibility in the selected current-sense
resistor value or inductor DCR, and allows smaller cur-
rent-sense resistance to be used, reducing the overall
power dissipated.
Steady-State Voltage Positioning
Connect a resistor (R FB ) between FB and V OUT to set
the DC steady-state droop (load line) based on the
required voltage-positioning slope (R DROOP ):
R DROOP
G
where the effective current-sense resistance (R SENSE )
depends on the current-sense method (see the Current
Sense section), and the voltage-positioning amplifier’s
transconductance (G m(FB) ) is typically 600 μS as
defined in the Electrical Characteristics table. The con-
troller sums together the input signals of the current-
sense inputs (CSP_, CSN_).
C BST_ =
2 × 24nC
200 mV
= 0 . 24 μF
When the inductors’ DCR is used as the current-sense
element (R SENSE = R DCR ), each current-sense input
should include an NTC thermistor to minimize the tem-
Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.
perature dependence of the voltage-positioning slope.
______________________________________________________________________________________
45
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