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参数资料
| 型号： | MB89PV630C-SH |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64 |
| 封装： | CERAMIC, MDIP-64 |
| 文件页数： | 102/153页 |
| 文件大小： | 7326K |
| 代理商： | MB89PV630C-SH |
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HARDWARE CONFIGURATION
2-29
(2) Description of functions
P00 to P07 CMOS-type I/O ports (also used as external-address/data bus)
P10 to P17 CMOS-type I/O ports (also used as external-address bus)
Operation when external bus extended
See the description of the bus functions.
Switching input and output
These ports have a data-direction register (DDR) and port-data register (PDR) for each bit. Input and
out put can be set independently for each bit. The pin with the DDR set to 1 is set to output, and the pin
with the DDR set to 0 is set to input. Note that the DDR is ineffective when the external bus is used.
Operation for output port (DDR = 1)
The value written at the PDR is output to the pin when the DDR is set to 1. When the PDR is read, usu-
ally, the value of the pin is read instead of the contents of the output latch. However, when the Read
Modify Write instruction is executed, the contents of the output latch are read irrespective of the DDR
setting con ditions. Therefore, the bit-processing instruction can be used even if input and output are
mixed with each other. When data is written to the PDR, the written data is held in the output latch irre-
spective of the DDR setting conditions.
Operation for input port (DDR = 0)
When settings the input, the output impedance goes High. Therefore, when the PDR is read, the value
of the pin is read.
State when reset
In the single-chip mode (MOD0 = Low, MOD1 = Low), the DDR is initialized to 0 by resetting and the out-
put impedance goes High at all bits. (Pins with activated pull-up resistors are in the pull-up state.) The
PDR is not initialized by resetting. Therefore, set the value of the PDR before setting the DDR to output.
State in stop mode
With the SPL bit of the standby-control register set to 1, in the stop mode, the output impedance goes
High irrespective of the value of the DDR. (Pins with activated pull-up resistors are in the pull-up state.)
Fig. 2.9 Ports 0 and 1 (in Single-chip Mode)
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相关代理商/技术参数 |
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