参数资料
型号: MB89PV630C-SH
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64
封装: CERAMIC, MDIP-64
文件页数: 146/153页
文件大小: 7326K
代理商: MB89PV630C-SH
HARDWARE CONFIGURATION
2-69
Transmission
When the next data is ready to write after data written to the serial output data register (SODR) is trans
ferred to the interrupt shift register, the TDRE (transmit data register empty) flag is set and an interrupt
request is output to the CPU.
Fig. 2.11 TDRE Flag Set Timing (Mode 0)
(c) Transfer data format
The UART can handle only NRZ (non-return-to-zero)-type data. The relationship between transmitter/re
ceiver clocks and data is shown in the figure below.
Fig. 2.4 Transfer Data Format
As shown in the figure, data transfer starts from the start bit (Low-level data), the data bit length specified by
the LSB first is transferred, and transfer ends at the stop bit (High-level data).
In asynchronous transfer, the relationship between UCK and SIN is not as shown in the above figure. In
addition, at asynchronous transfer, the relationship is not as shown in the above diagram even when UCK is
set to input.
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