参数资料
型号: MB89PV630C-SH
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64
封装: CERAMIC, MDIP-64
文件页数: 153/153页
文件大小: 7326K
代理商: MB89PV630C-SH
MB89630 SERIES HARDWARE MANUAL
2-76
(4) Description of operation
(a) Outline
This module consists of the serial-mode register (SMR) and serial-data register (SDR). At serial output,
data in the SDR is output in bit serial to the serial output pin (SO) in synchronization with the falling edge of
a serial shift-clock pulse generated from the internal or external clock. At serial input, data is input in bit
serial from the serial input pin (SI) to the SDR at the rising edge of a serial shift-clock pulse.
(b) Operation modes
The serial I/O has three internal shift-clock modes and one external shift-clock mode, which are specified
by the SMR. Mode switching or clock selection should be made with serial I/O stopped (SST bit (bit 0) of
SMR = 0).
(1) Internal shift-clock mode
Operation is performed by the internal clock. A shift-clock pulse with a duty of 50% is output from the
SCK pin as a synchronous timing output. Data is transferred bit-by-bit at every clock pulse.
(2) External shift-clock mode
Data is transferred bit-by-bit at every clock pulse in synchronization with the external shift-clock pulse
input from the SCK pin. If an external clock is input when the SST bit is set to 0, no shift operation
occurs and data of the SDR register (or the value of bit 7 when MSB first used) is output to the SO
pin. However, the pin value is also rewritten when the SDR register data is rewritten. The transfer
speed can be from DC to 1/2 oscillation (two instruction cycles). When one instruction cycle is 0.4
s
(at 10 MHz oscilla tion), the transfer speed can be up to 1.25 MHz.
Do not write data to the SMR and SDR during the serial I/O operation in either mode.
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