参数资料
型号: MB89PV630C-SH
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64
封装: CERAMIC, MDIP-64
文件页数: 3/153页
文件大小: 7326K
代理商: MB89PV630C-SH
HARDWARE CONFIGURATION
2-77
(c) Interrupt functions
This module can output an interrupt request to the CPU. To output an interrupt request, set the SIOE bit (bit
6) of the SMR to 1 to enable an interrupt and then set the interrupt flag SIOF (bit 7) of SMR after 8-bit data
transfer is terminated.
(d) Shift start/stop timing
Data transfer starts when 1 is written at the SST bit (bit 0) of the SMR, and stops when 0 is written. When
data transfer is terminated, the SST bit is automatically cleared to 0, which stops the operation.
(1) Internal shift-clock mode (LSB first)
[When transfer terminated]
[When transfer suspended]
(2) External shift-clock mode (LSB first)
[When transfer terminated]
[When transfer suspended]
Note: When data is written at the SDR, the output data changes at the falling edge of the external-clock
pulse.
Fig. 2.12 Shift Start/Stop Timing
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