参数资料
型号: MB89PV630C-SH
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64
封装: CERAMIC, MDIP-64
文件页数: 36/153页
文件大小: 7326K
代理商: MB89PV630C-SH
OPERATION
3-11
3.5.2 Hold Function
The CPU samples the user hold-request input to the HRQ pin at the boundary of each instruction and sets
the HAK pin to Low to open the bus. When the CPU detects that the HRQ pin is active, it temporarily sus-
pends operation to set the address, data, RD, WR, and BUFC pins to High impedance, and also enters the
hold state after outputting a Low level from the HAK pin. Figure 3.9 shows the hold timing.
Fig. 3.23 Hold Timing
The CPU does not accept any hold requests in the stop and sleep modes. The use of the hold-acknowl-
edge signal with an external buffer is shown in Figure 3.6.
In the hold mode, the CPU is stopped but each resource is operable. No watchdog reset occurs during the
hold mode because the watchdog timer counter is cleared.
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