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参数资料
| 型号： | MB9AF312NPMC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 16/114页 |
| 文件大小： | 1357K |
| 代理商： | MB9AF312NPMC |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
112
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in
OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
Figure 16-8 on page 112. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The
TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches
between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs.
Figure 16-8. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is
used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x
registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each
time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between
the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1x registers are written. As the third period shown in Figure 16-8 on page 112 illustrates, changing the TOP actively
while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can
be found in the time of update of the OCR1x register. Since the OCR1x update occurs at TOP, the PWM period starts and
ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the
rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in
length. The difference in length gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP
value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the
two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the
COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the
COM1x1:0 to three (See Table on page 117). The actual OC1x value will only be visible on the port pin if the data direction
for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x register at
the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x register at
compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using
phase correct PWM can be calculated by the following equation:
1
2
34
TCNTn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCnx
Period
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCRnx/ TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
fOCnxPCPWM
fclk_I/O
2N
×
TOP
×
-------------------------------
=
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