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参数资料
| 型号： | MB9AF314NBGL |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PBGA112 |
| 封装： | 0.80 MM PITCH, PLASTIC, FBGA-112 |
| 文件页数： | 41/114页 |
| 文件大小： | 1357K |
| 代理商： | MB9AF314NBGL |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
32
9.9
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to be programmed.
This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during
reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the
internal RC oscillator, can be selected when the clock is output on CLKO. If the system clock prescaler is used, it is the
divided system clock that is output.
9.10
Timer/Counter Oscillator
The Atmel ATmega48PA/88PA/168PA uses the same crystal oscillator for low-frequency oscillator and Timer/Counter
oscillator. See Section 9.5 “Low Frequency Crystal Oscillator” on page 28 for details on the oscillator and crystal
requirements.
Atmel ATmega48PA/88PA/168PA share the Timer/Counter oscillator pins (TOSC1 and TOSC2) with XTAL1 and XTAL2.
When using the Timer/Counter oscillator, the system clock needs to be four times the oscillator frequency. Due to this and
the pin sharing, the Timer/Counter oscillator can only be used when the calibrated Internal RC oscillator is selected as
system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR register is written to logic one.
See Section 18.9 “Asynchronous Operation of Timer/Counter2” on page 135 for further description on selecting external
clock as input instead of a 32.768kHz watch crystal.
9.11
System Clock Prescaler
The Atmel ATmega48PA/88PA/168PA has a system clock prescaler, and the system clock can be divided by setting the
Section 9.12.2 “CLKPR – Clock Prescale Register” on page 33. This feature can be used to decrease the system clock
frequency and the power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and
When switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system.
It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at
the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to
determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to
the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2
before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock
period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:
1.
Write the clock prescaler change enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
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