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参数资料
| 型号： | MB9AF314NBGL |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PBGA112 |
| 封装： | 0.80 MM PITCH, PLASTIC, FBGA-112 |
| 文件页数： | 6/114页 |
| 文件大小： | 1357K |
| 代理商： | MB9AF314NBGL |
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103
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
16.5
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block
diagram of the counter and its surroundings.
Figure 16-2. Counter Unit Block Diagram
Signal description (internal signals):
Count
Increment or decrement TCNT1 by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNT1 (set all bits to zero).
clkT1
Timer/Counter clock.
TOP
Signalize that TCNT1 has reached maximum value.
BOTTOM
Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter high (TCNT1H) containing the upper eight bits of
the counter, and counter low (TCNT1L) containing the lower eight bits. The TCNT1H register can only be indirectly accessed
by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register
(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with
the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value
within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1
register when the counter is counting that will give unpredictable results. The special cases are described in the sections
where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1).
The clkT1 can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no
clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU,
independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the waveform generation mode bits (WGM13:0) located in the
Timer/Counter control registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the output compare outputs OC1x. For more details about
advanced counting sequences and waveform generation, see Section 16.9 “Modes of Operation” on page 108.
The Timer/Counter overflow flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can
be used for generating a CPU interrupt.
BOTTOM
TOP
TOVn
(Int. Req.)
DATA BUS (8-bit)
Control Logic
TCNTnH (8-bit)
TCNTnH (16-bit Counter)
TCNTnL (8-bit)
TEMP (8-bit)
clkTn
Clear
Count
Direction
Edge
Detector
(from Prescaler)
Clock Select
Tn
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