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参数资料
| 型号： | MBM29LV160BE12PBT-E1 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 2M X 8 FLASH 3V PROM, 120 ns, PBGA48 |
| 封装： | PLASTIC, FBGA-48 |
| 文件页数： | 11/59页 |
| 文件大小： | 759K |
| 代理商： | MBM29LV160BE12PBT-E1 |
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MBM29LV160TE/BE-70/90/12
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Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occures during the
programming operation, it is impossible to guarantee whether the data being written is correct or not.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 20 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls
or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read mode.
(See Figure 8.)
Figure 21 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”
command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address
(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data
= 30H) is latched on the rising edge of WE. After a time-out of “tTOW” from the rising edge of the last sector erase
command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing six-bus cycle operations on Table 7. This sequence is
followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW”
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the “tTOW” time-out window the timer is reset. Monitor DQ3 to determine if the sector
erase timer window is still open. (See section DQ3, Sector Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous
command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case,
restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for
Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 34).
Sector erase does not require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the “tTOW” time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
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相关代理商/技术参数 |
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| MBM29LV160BE12PCV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29LV160BE12TN | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29LV160BE12TR | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29LV160BE-70 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
| MBM29LV160BE70PBT | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M X 8/1M X 16) BIT |
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