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参数资料
| 型号： | MC10XS3412DPNA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 28/55页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HIGH SIDE QUAD 24QFN |
| 标准包装： | 168 |
| 类型： | 高端开关 |
| 输出数： | 4 |
| Rds（开）： | 2 x 10 毫欧，2 x 12 毫欧 |
| 内部开关： | 是 |
| 电流限制： | 5A |
| 输入电压： | 4 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 托盘 |
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SLEEP MODE
The 10XS3412 is in Sleep mode when:
? V PWR and V DD are within the normal voltage range,
? wake-up = 0,
The timing includes seven programmable PWM switching
delay (number of PWM clock rising edges) to improve overall
EMC behavior of the light module ( Table 8 ).
Table 8. Output PWM Switching Delay
? fail = X,
? fault = X.
This is the Default mode of the device after first applying
battery voltage (VPWR) prior to any I/O transitions. This is
also the state of the device when the WAKE and RST and
IN_ON[0:3] are logic [0]. In the Sleep mode, the output and
all unused internal circuitry, such as the internal regulator, are
off to minimize draw current. In addition, all SPI-configurable
features of the device are as if set to logic [0].
NORMAL MODE
Delay bits
000
001
010
011
100
101
110
111
Output delay
no delay
16 PWM clock periods
32 PWM clock periods
48 PWM clock periods
64 PWM clock periods
80 PWM clock periods
96 PWM clock periods
112 PWM clock periods
The 10XS3412 is in Normal mode when:
? V PWR and V DD are within the normal voltage range,
? wake-up = 1,
? fail = 0,
? fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and
the outputs HS[0:3] are under control, as defined by hson
signal:
hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en
) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset
depends on fault_control signal, as defined below:
fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en )
or (On bit [x]).
Programmable PWM module
The outputs HS[0:3] are controlled by the programmable
PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from IN0 input pin or from internal
clock is the factor 2 7 (128) of the output PWM frequency
(CLOCK_sel bit). The outputs HS[0:3] can be controlled in
the range of 5% to 98% with a resolution of 7 bits of duty cycle
The clock frequency from IN0 is permanently monitored in
order to report a clock failure in case of the frequency is out
a specified frequency range (from f IN0(LOW) to f IN0(HIGH) ). In
case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
Calibratable internal clock
The internal clock can vary as much as +/-30 percent
corresponding to typical f PWM(0) output switching period.
Using the existing SPI inputs and the precision timing
reference already available to the MCU, the 10XS3412
allows clock period setting within +/-10 percent of accuracy.
Calibrating the internal clock is initiated by defined word to
CALR register. The calibration pulse is provided by the MCU.
The pulse is sent on the CS pin after the SPI word is
launched. At the moment, the CS pin transitions from logic [1]
to [0] until from logic [0] to [1] determine the period of internal
clock with a multiplicative factor of 128.
CS
SI
Table 7. Output PWM Resolution
CALR
SI command
ignored
On bit
Duty cycle
Output state
0
1
1
1
1
1
X
0000000
0000001
0000010
n
1111111
OFF
PWM (1/128 duty cycle)
PWM (2/128 duty cycle)
PWM (3/128 duty cycle)
PWM ((n+1)/128 duty cycle)
fully ON
Internal
clock duration
In case of negative CS pulse is outside a predefined time
range (from t CSB(MIN) to t CSB(MAX) ), the calibration event will
be ignored and the internal clock will be unaltered or reset to
default value (f PWM(0) ) if this was not calibrated before.
The calibratable clock is used, instead of the clock from
IN0 input, when CLOCK_sel is set to [1].
10XS3412
Analog Integrated Circuit Device Data ?
28
Freescale Semiconductor
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