参数资料
型号: MC10XS3412DPNA
厂商: Freescale Semiconductor
文件页数: 50/55页
文件大小: 0K
描述: IC SWITCH HIGH SIDE QUAD 24QFN
标准包装: 168
类型: 高端开关
输出数: 4
Rds(开): 2 x 10 毫欧,2 x 12 毫欧
内部开关:
电流限制: 5A
输入电压: 4 V ~ 28 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-PowerQFN
供应商设备封装: 24-PQFN(12x12)
包装: 托盘
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the 10XS3412
technical data sheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application and packaging information is
provided in the data sheet.
Package and Thermal Considerations
This 10XS3412 is a dual die package. There are two heat sources in the
package independently heating with P 1 and P 2 . This results in two junction
temperatures, T J1 and T J2 , and a thermal resistance matrix with R ? JA mn .
For m , n = 1, R ? JA11 is the thermal resistance from Junction 1 to the
reference temperature while only heat source 1 is heating with P 1 .
For m = 1, n = 2, R ? JA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P 2 . This applies
to R ? J21 and R ? J22 , respectively.
10XS3412
24-PIN
PQFN
98ARL10596D
24-PIN PQFN (12 x 12)
Note For package dimensions, refer to
T J1
T J2
=
R ? JA11
R ? JA21
R ? JA12
R ? JA22
.
P 1
P 2
98ARL10596D.
The stated values are solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to
the standards listed below.
Standards
Table 25. Thermal Performance Comparison
Thermal
1 = Power Chip, 2 = Logic Chip [ ? C/W]
Resistance
R ? JA mn (1)(2)
R ? JB mn (2)(3)
m = 1,
n =1
26.04
13.21
m = 1, n = 2
m = 2, n = 1
18.18
6.40
m = 2,
n =2
35.49
23.94
R ? JA mn (1)(4)
R ? JC mn (5)
46.42
0.67
37.03
0.95
53.82
0.00
0.2mm
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and ?
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
0.2mm
0.5mm dia.
Figure 15. Detail of Copper Traces Under Device with
Thermal Vias
10XS3412
Analog Integrated Circuit Device Data ?
50
Freescale Semiconductor
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