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| 型号： | MC10XS3412DPNA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 33/55页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HIGH SIDE QUAD 24QFN |
| 标准包装： | 168 |
| 类型： | 高端开关 |
| 输出数： | 4 |
| Rds（开）： | 2 x 10 毫欧，2 x 12 毫欧 |
| 内部开关： | 是 |
| 电流限制： | 5A |
| 输入电压： | 4 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 托盘 |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
forward mode. No additional passive components are
required except on VDD current path.
GROUND DISCONNECT PROTECTION
In the event the 10XS3412 ground is disconnected from
load ground, the device protects itself and safely turns OFF
the output regardless of the state of the output at the time of
disconnection (maximum VPWR=16 V). A 10 k ? resistor
needs to be added between the MCU and each digital input
pin in order to ensure that the device turns off in case of
ground disconnect and to prevent this pin from exceeding
maximum ratings.
LOSS OF SUPPLY LINES
Loss of VDD
If the external VDD supply is disconnected (or not within
specification: V DD <V DD(FAIL)) with VDD_FAIL_en bit is set to
logic [1]), all SPI register content is reset.
The outputs can still be driven by the direct inputs IN[0 : 3]
if V PWR is within specified voltage range. The 10XS3412
uses the battery input to power the output MOSFET-related
current sense circuitry and any other internal logic providing
Fail Safe device operation with no V DD supplied. In this state,
the overtemperature, overcurrent, severe short-circuit, short
to VPWR and OFF open-load circuitry are fully operational
Loss of VPWR
If the external VPWR supply is disconnected (or not within
specification), the SPI configuration, reporting, and daisy
chain features are provided for RST is set to logic [1] under
V DD in nominal conditions. The SPI pull-up and pull-down
current sources are not operational. This fault condition can
be diagnosed with UV fault in the SPI STATR_s registers.
The previous device configuration is maintained. No current
is conducted from VDD to VPWR.
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected
(or not within specification: (VDD and VPWR) <
V SUPPLY(POR) ), all SPI register contents are reset with default
values corresponding to all SPI bits are set to logic [0] and all
latched faults are also reset.
EMC PERFORMANCES
All following tests are performed on Freescale evaluation
board in accordance with the typical application schematic.
The device is protected in case of positive and negative
transients on the VPWR line (per ISO 7637-2).
The 10XS3412 successfully meets Class 5 of the
CISPR25 emission standard, and 200 V/m or BCI 200 mA
injection level for immunity tests.
with default values corresponding to all SPI bits are set to
logic [0]. No current is conducted from VPWR to V DD .
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 ( Table 10 ).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit (WDIN). In some cases, output
selection is done with bits D14 : D13. The next three bits,
D12: D10, are used to select the command register. The
remaining nine bits, D8 : D0, are used to configure and control
the outputs and their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 10XS3412 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 11 summarizes the SI registers.
Table 10. SI Message Bit Assignment
Bit Sig
MSB
LSB
SI Msg Bit
D15
D14 : D13
D12 : D10
D9
D8:D0
Message Bit Description
Watchdog in: toggled to satisfy watchdog requirements.
Register address bits used in some cases for output selection ( Table 12 ).
Register address bits.
Not used (set to logic [0]).
Used to configure the inputs, outputs, and the device protection features and SO status content.
10XS3412
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
33
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