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参数资料
| 型号： | MC10XS3412DPNA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 31/55页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HIGH SIDE QUAD 24QFN |
| 标准包装： | 168 |
| 类型： | 高端开关 |
| 输出数： | 4 |
| Rds（开）： | 2 x 10 毫欧，2 x 12 毫欧 |
| 内部开关： | 是 |
| 电流限制： | 5A |
| 输入电压： | 4 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 托盘 |
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FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Overvoltage Fault (Enabled by default)
By default, the overvoltage protection is enabled. The
10XS3412 shuts down all outputs and FS will go to logic [0]
during an overvoltage fault condition on the VPWR pin (V PWR
> V PWR(OV) ). The outputs remain in the OFF state until the
overvoltage condition is removed (V PWR < V PWR(OV) -
V PWR(OVHYS) ). When experiencing this fault, the OVF fault bit
is set to logic [1] and cleared after either a valid SPI read.
The overvoltage protection can be disabled through SPI
(OV_dis bit is disabled set to logic [1]). The fault register
reflects any overvoltage condition (V PWR > V PWR(OV) ). This
overvoltage diagnosis, as a warning, is removed after a read
operation, if the fault condition disappears. The HS[0:3]
outputs are not commanded in R DS(ON) above the OV
threshold.
In Fail-safe mode, the overvoltage activation depends on
the RST logic state: enable for RST = 1 and disable for
RST = 0. The device is still protected with overtemperature
protection in case the overvoltage feature is disabled.
Undervoltage Fault
The output(s) will latch off at some battery voltage below
VPWR (UV) . As long as the V DD level stays within the normal
specified range, the internal logic states within the device will
remain (configuration and reporting).
In the case where battery voltage drops below the
undervoltage threshold (V PWR < V PWR(UV) ), the outputs will
turn off, FS will go to logic [0], and the fault register UV bit will
be set to [1].
Two cases need to be considered when the battery level
recovers (VPWR > VPWR(UV)_UP):
? If outputs command are low, FS will go to logic [1] but
the UV bit will remain set to 1 until the next read
operation (warning report).
? If the output command is ON, FS will remain at logic [0].
To delatch the fault and be able to turn ON again the
outputs, the failure condition must disappear and the
autoretry circuitry must be active or the corresponding
output must be commanded OFF and then ON (toggling
fault_control signal of corresponding output) or
V SUPPLY(POR) condition if V DD = 0.
In extended mode , the output is protected by
overtemperature shutdown circuitry. All previous latched
faults, occurred when VPWR was within the normal voltage
range, are guaranteed if VDD is within the operational voltage
range or until V SUPPLY(POR) if VDD = 0. Any new OT fault is
detected (VDD failure included) and reported through SPI
above VPWR (UV) . The output state is not changed as long as
the VPWR voltage does not drop any lower than 3.5 V typical.
All latched faults (overtemperature, overcurrent, severe
short-circuit, over and undervoltage) are reset if:
? V DD < V DD(FAIL) with V PWR in nominal voltage range,
? V DD and V PWR supplies is below V SUPPLY(POR) voltage
value.
(fault_control=0)
(Open-load OFF=1
or ShortVpwr=1
or OV=1)
(fault_control=1 and OV=0)
(Open-load ON=1)
(open-loadOFF=1
or ShortVpwr=1
or OV=1)
OFF
if hson=0
(fault_control=0 or OV=1)
(fault_control=0)
ON
if hson=1
(Retry=1)
(SC=1)
(count=16)
Latched
OFF
(SC=1)
(after Retry Period and OV=0)
(Open-load ON=1)
Auto-retry
OFF
(Open-load OFF=1
or ShortVpwr=1
(OV=1)
(Retry=1)
=> count=count+1
Auto-retry
ON
if hson=1
or OV=1)
(fault_control=0)
Figure 12. Autoretry State Machine
10XS3412
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
31
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