参数资料
型号: MC10XS3412DPNA
厂商: Freescale Semiconductor
文件页数: 36/55页
文件大小: 0K
描述: IC SWITCH HIGH SIDE QUAD 24QFN
标准包装: 168
类型: 高端开关
输出数: 4
Rds(开): 2 x 10 毫欧,2 x 12 毫欧
内部开关:
电流限制: 5A
输入电压: 4 V ~ 28 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-PowerQFN
供应商设备封装: 24-PQFN(12x12)
包装: 托盘
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is
Xenon bit set to logic [0]:
I OCH1
replaced by OCHI2 during t OC1 , as shown Figure 14 .
I OCH1
I OCH2
I OC1
I OC2
I OCLO4
I OCLO3
I OCLO2
I OCLO1
t OC1 t OC3 t OC4 t OC5
t OC2
Xenon bit set to logic [1]:
t OC6
t OC7
Time
I OCH2
I OC1
I OC2
I OC3
I OC4
I OCLO4
I OCLO3
I OCLO2
I OCLO1
t OC1 t OC3 t
t OC2
OC4
t OC5
t OC6
t OC7
Time
Figure 14. Overcurrent profile with OCHI bit set to ‘1’
I OCH1
I OCH2
I OC1
I OC2
I OC3
I OC4
I OCLO4
I OCLO3
I OCLO2
I OCLO1
The wire harness is protected by one of four possible
current levels in steady state, as defined in Table 18 .
Table 18. Output Steady State Selection
OCLO1 (D2) OCLO0 (D1) Steady State Current
0 0 OCLO2 (default)
0 1 OCLO3
t OC1 t OC3 t
t OC2
OC4
t OC5
t OC6
t OC7
Time
1
1
0
1
OCLO4
OCLO1
Figure 13. Overcurrent profile depending on Xenon bit
D[7:6] bits allow to MCU to programmable bulb cooling
curve and D[5:4] bits inrush curve for selected output, as
shown Table 16 and Table 17 .
Bit D0 (OC_mode_sel) allows to select the overcurrent
mode, as described Table 19 .
Table 19. Overcurrent Mode Selection
OC_mode_s (D0) Overcurrent Mode
Table 16. Cooling Curve Selection
0
only inrush current management (default)
BC1_s (D7)
BC0_s (D6)
Profile Curves Speed
1
inrush current and bulb cooling
0
0
1
1
0
1
0
1
medium (default)
slow
fast
medium
management
ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
The GCR register allows the MCU to configure the device
Table 17. Inrush Curve Selection
OC1_s (D5) OC0_s (D4)
0 0
Profile Curves Speed
slow (default)
through the SPI.
Bit D8 allows the MCU to enable or disable the V DD failure
detector. A logic [1] on VDD_FAIL_en bit allows transitioning
to Fail-safe mode for V DD < V DD(FAIL).
Bit D7 allows the MCU to enable or disable the PWM
0
1
1
1
0
1
fast
medium
very slow
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as
reference by PWM module, as described in the following
10XS3412
Analog Integrated Circuit Device Data ?
36
Freescale Semiconductor
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