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| 型号： | MC33874BPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 11/38页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HI SIDE 35MOHM 24PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 4 |
| 导通状态电阻： | 35 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ V PWR ≤ 27V, 4.5V ≤ V DD ≤ 5.5V, - 40 ° C ≤ T A ≤ 125 ° C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued)
Over-current High Detection Blanking Time
CS to CSNS Valid Time (24)
t OCH
t CNSVAL
1.0
–
5.0
–
20
10
μ s
μ s
Watchdog
Timeout (25)
ms
WD[1:0] : 00
WD[1:0] : 01
WD[1:0] : 10
WD[1:0] : 11
t WDTO0
t WDTO1
t WDTO2
t WDTO3
446
223
1800
900
558
279
2250
1125
725
363
2925
1463
Direct Input Switching Frequency (DICR D3 = 0)
f PWM
-
300
-
Hz
SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO)
Required Low-state Duration for RST
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Maximum Frequency of SPI Operation
(26)
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (27)
(27)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (27)
f SPI
t WRST
t CS
t ENBL
t LEAD
–
–
–
–
–
–
50
–
–
50
3.0
350
300
5.0
167
MHz
ns
ns
μ s
ns
Required High-state Duration of SCLK (Required Setup Time)
(27)
t WSCLKh
–
–
167
ns
Required Low-state Duration of SCLK (Required Setup Time) (27)
t WSCLKl
–
–
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time) (28)
(27)
t LAG
t SI (SU)
–
–
50
25
167
83
ns
ns
Falling Edge of SCLK to SI (Required Setup Time)
(28)
t SI (HOLD)
–
25
83
ns
SO Rise Time
t RSO
ns
C L = 200pF
SO Fall Time
C L = 200pF
t FSO
–
–
25
25
50
50
ns
SI, CS , SCLK, Incoming Signal Rise Time (28)
SI, CS , SCLK, Incoming Signal Fall Time (28)
t RSI
t FSI
–
–
–
–
50
50
ns
ns
Time from Falling Edge of CS to SO
Low-impedance (29)
t SO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High-impedance (30)
(31)
Time from Rising Edge of SCLK to SO Data Valid
0.2 V DD ≤ SO ≤ 0.8 x V DD , C L = 200pF
t SO(DIS)
t VALID
–
–
65
65
145
105
ns
ns
Notes
24. Time necessary for the CSNS to be with ±5% of the targeted value.
25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t WDTO is consistent for all configured
watchdog timeouts.
26.
RST low duration measured with outputs enabled and going to OFF or disabled condition.
27. Maximum setup time required for th e 33874 is the minimum guaranteed time needed from the microcontroller.
28. Rise and Fall time of incoming SI, CS , and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
29. Time required for output status data to be available for use at SO. 1.0k Ω on pull-up on CS .
30. Time required for output status data to be terminated at SO. 1.0k Ω on pull-up on CS .
31. Time required to obtain valid data out from SO following the rise of SCLK.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
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