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| 型号： | MC33874BPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 22/38页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HI SIDE 35MOHM 24PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 4 |
| 导通状态电阻： | 35 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 ( Table 8 ).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit. In some cases, output selection is
done with bits D12 : D11. The next three bits, D10 : D8, are
used to select the command register. The remaining five bits,
D4 : D0, are used to configure and control the outputs and
their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 33874 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 8. SI Message Bit Assignment
Bit Sig
MSB
LSB
SI Msg Bit
D15
D14 : D15
D12 : D11
D10 : D8
D7 : D5
D4 : D1
D0
Message Bit Description
Watchdog in: toggled to satisfy watchdog requirements.
Not used.
Register address bits used in some cases for output selection.
Register address bits.
Not used.
Used to configure the inputs, outputs, and the device protection features and SO status content.
Used to configure the inputs, outputs, and the device protection features and SO status content.
Table 9. Serial Input Address and Configuration Bit Map
SI Data
SI Register
D15
D14 D13 D12 D11 D10 D9
D8 D7 D6 D5
D4
D3
D2
D1
D0
STATR_s
OCR0
OCR1
WDIN
WDIN
WDIN
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
SOA4
0
0
SOA3
IN3_SPI
CSNS3 EN
SOA2
IN2_SPI
CSNS2 EN
SOA1
IN1_SPI
CSNS1 EN
SOA0
IN0_SPI
CSNS0 EN
SOCHLR_s WDIN
CDTOLR_s WDIN
0
0
0
0
A 1
A 1
A 0
A 0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
SOCH_s
OL_DIS_s
SOCL2_s
OCL_DIS_s
SOCL1_s
OCLT1_s
SOCL0_s
OCLT0_s
DICR_s
WDIN
0
0
A 1
A 0
1
0
0
0
0
0
0
FAST_SR_s
CSNS_high_s DIR_DIS_s
A/O_s
UOVR
WDR
WDIN
WDIN
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
OT_latch-1
OT_latch_3
OT_latch_0
OT_latch_2
UV_DIS
WD1
OV_DIS
WD0
NAR
WDIN
0
0
0
0
1
1
0
0
0
0
0
No Action (Allow Toggling of D15 - WDIN)
RESET
0
0
0
X
X
X
X
X
0
0
0
0
0
0
0
0
x = Don’t care.
D15 is used to toggle watchdog event (WDIN)
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses and their impact on device operation.
ADDRESS 00000 — STATUS REGISTER (STATR_S)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the OCR0, OCR1, SOCHLR,
33874
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
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