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| 型号： | MC33874BPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 20/38页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HI SIDE 35MOHM 24PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 4 |
| 导通状态电阻： | 35 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
detection levels, defined by I OCH and I OCL , are illustrated in
If the load current level ever reaches the selected over-
current low detection level and the over-current condition
exceeds the programmed over-current time period (t OC x ), the
device will latch the output OFF.
If at any time the current reaches the selected I OCH level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected t OCH driver.
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
OVER-VOLTAGE FAULT (NON-LATCHING)
The 33874 shuts down the output during an over-voltage
fault (OVF) condition on the VPWR pin. The output remains
in the OFF state until the over-voltage condition is removed.
When experiencing this fault, the OVF fault bit is set in the bit
D1 and cleared after either a valid SPI read or a power reset
of the device.
The over-voltage protection can be disabled through SPI
(bit OV_DIS). When disabled, the returned SO bit OD13 still
reflects any over-voltage condition (over-voltage warning).
UNDER-VOLTAGE SHUTDOWN (LATCHING OR
NON-LATCHING)
The output(s) will latch off at some battery voltage below
6.0 V. As long as the V DD level stays within the normal
specified range, the internal logic states within the device will
be sustained.
In the case where battery voltage drops below the under-
voltage threshold (V PWRUV ) output will turn off, FS will go to
logic 0, and the fault register UVF bit will be set to 1.
Two cases need to be considered when the battery level
recovers :
? If outputs command are low, FS will go to logic 1 but the
UVF bit will remain set to 1 until the next read operation
(warning report).
? If the output command is ON, then FS will remain at
logic 0. The output must be turned OFF and ON again
to re-enable the state of output and release FS. The
UVF bit will remain set to 1 until the next read operation.
The under-voltage protection can be disabled through SPI
(bit UV_dis = 1). In this case, the FS does not report any
under-voltage fault condition, UVF bit is set to 1, and the
output state is not changed as long as the battery voltage
does not drop any lower than 2.5 V.
The daisy chain feature is available under VDD in nominal
conditions.
33874
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
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