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| 型号： | MC33874BPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 23/38页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HI SIDE 35MOHM 24PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 4 |
| 导通状态电阻： | 35 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to
the section entitled Serial Output Communication (Device
Table 11. Over-current Low Detection Levels
Status Return Data) beginning on page 24 .)
SOCL2_s * SOCL1_s * SOCL0_s *
Over-current Low
Detection (Amperes)
ADDRESS 00001— OUTPUT CONTROL REGISTER
(OCR0 )
The OCR0 register allows the MCU to control the ON / OFF
state of four outputs through the SPI. Incoming message bit
D3 : D0 reflects the desired states of the four high side outputs
(INx_SPI), respectively. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF.
ADDRESS 01001— OUTPUT CONTROL REGISTER
(OCR1 )
Incoming message bits D3 : D0 reflect the desired output
that will be mirrored on the Current Sense (CSNS) pin. A
(D2)
0
0
0
0
1
1
1
1
(D1)
0
0
1
1
0
0
1
1
(D0)
0
1
0
1
0
1
0
1
HS0 to HS3
10
8.9
7.9
7.0
5.8
4.8
3.9
2.8
logic [1] on message bits D3 : D0 enables the CSNS pin for
outputs HS3 : HS0, respectively. In the event the current
sense is enabled for multiple outputs, the current will be
summed. In the event that bits D3 : D0 are all logic [0], the
output CSNS will be tri-stated. This is useful when several
* “_s” refers to the output, which is selected through bits D12 : D11;
Table 12. Over-current High Detection Levels
CSNS pins of several devices share the same A /D converter.
ADDRESS A 1 A 0 010 — SELECT OVER-CURRENT
HIGH AND LOW REGISTER (SOCHLR_S)
The SOCHLR_s register allows the MCU to configure the
SOCH_s * (D3)
0
1
Over-current High Detection (Amperes)
HS0 to HS3
55
40
output over-current low and high detection levels,
respectively. Each output “s” is independently selected for
configuration based on the state of the D12 : D11 bits
Table 10. Output Selection
* “_s” refers to the output, which is selected through bits D12 : D11;
ADDRESS A 1 A 0 011 — CURRENT DETECTION TIME
AND OPEN LOAD REGISTER (CDTOLR)
A 1 (D12)
0
0
1
1
A 0 (D11)
0
1
0
1
HS_s
HS0
HS1
HS2
HS3
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an over-current low
condition before an output latches OFF. Each output is
independently selected for configuration based on A 1 A 0 ,
Bits D1 : D0 (OCLT1_s : OCLT0_s) allow the MCU to select
Each output can be configured to different levels. In
addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements matching system characteristics. Bits D2 : D0
set the over-current low detection level to one of eight
possible levels, as shown in Table 11 , page 23 . Bit D3 sets
one of three over-current fault blanking times defined in
current low detection levels. If the selected over-current high
level is reached, the device will latch off within 20 μ s .
Table 13. Over-current Low Detection Blanking Time
the over-current high detection level to one of two levels, as
OCLT[1:0]_s *
00
01
10
11
Timing
155ms
Do not use
75ms
150 μ s
* “_s” refers to the output, which is selected through bits D12 : D11;
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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