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| 型号： | MC33874BPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 34/38页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HI SIDE 35MOHM 24PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 4 |
| 导通状态电阻： | 35 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the 33874 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
Packaging and Thermal Considerations
This package is a dual die package. There are two heat sources in the package
independently heating with P 1 and P 2 . This results in two junction temperatures,
T J1 and T J2 , and a thermal resistance matrix with R θ JA mn .
For m , n = 1, R θ JA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P 1 .
For m = 1, n = 2, R θ JA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P 2 . This applies to R θ J21
and R θ J22 , respectively.
33874
HIGH SIDE SWITCH
PNA SUFFIX
98ART10510D
24-PIN PQFN (12 x 12)
T J1
T J2
=
R θ JA11
R θ JA21
R θ JA12
R θ JA22
.
P 1
P 2
Note For package dimensions, refer to
the 33874 data sheet.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained
by measurement and simulation according to the standards listed below.
Table 18. Thermal Performance Comparison
Thermal
1 = Power Chip, 2 = Logic Chip [ ° C/W]
Resistance
m = 1,
m = 1, n = 2
m = 2,
n =1
m = 2, n = 1
n =2
1.0
R θ JA mn
(1) , (2)
R θ JB mn (2) , (3)
R θ JA mn (1) , (4)
R θ JC mn (5)
20
6
53
<0.5
16
2.0
40
0.0
39
26
73
1.0
0.2
1.0
0.2
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Figure 10. Testboard According to JEDEC
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
33874
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
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