参数资料
型号: MC33874BPNAR2
厂商: Freescale Semiconductor
文件页数: 21/38页
文件大小: 0K
描述: IC SW QUAD HI SIDE 35MOHM 24PQFN
标准包装: 1,200
类型: 高端
输入类型: SPI
输出数: 4
导通状态电阻: 35 毫欧
电源电压: 6 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-PowerQFN
供应商设备封装: 24-PQFN(12x12)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Table 7. Device behavior in case of Under-voltage
Quad High Side
Switch
(VPWR Battery
Voltage) ??
State
UV Enable UV Enable UV Enable UV Enable
IN[0:3] = 0 IN[0:3] = 0 IN_x*** = 1 IN_x*** = 1
(Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR)
UV Disable UV Disable
IN[0:3] = 0 IN_x*** = 1
(Falling or (Falling or
Rising VPWR) Rising VPWR)
VPWR > VPWRUV
Output State
FS State
SPI Fault Register
OFF
1
0
OFF
1
1 until next read
ON
1
0
OFF
0
1
OFF
1
0 (falling)
ON
1
0 (falling)
UVF Bit
1 until next
read (rising)
1 until next
read (rising)
VPWRUV > VPWR
> UVPOR
Output State
FS State
SPI Fault Register
OFF
0
1
OFF
0
1
OFF
0
1
OFF
0
1
OFF
1
1
ON
1
1
UVF Bit
UVPOR > VPWR >
2.5V ?
Output State
FS State
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
ON
1
SPI Fault Register 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read
UVF Bit
2.5V > VPWR > 0V
Output State
FS State
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
SPI Fault Register 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read
UVF Bit
Comments
UV fault is
not latched
UV fault is
not latched
UV fault
is latched
? = Typical value; not guaranteed
?? = While V DD remains within specified range.
*** = IN_x is equivalent to IN_x direct input or IN_spi_s SPI input.
OPEN LOAD FAULT (NON-LATCHING)
The 33874 incorporates open load detection circuitry on
the output. Output open load fault (OLF) is detected and
reported as a fault condition when the output is disabled
(OFF). The open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OLF fault bit is set in the
status register. If the open load fault is removed, the status
register will be cleared after reading the register.
The open load protection can be disabled through SPI
(bit OL_DIS). It is recommended to disable open load
circuitry in case of a permanent disconnected load.
REVERSE BATTERY
The output survives the application of reverse voltage as
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are
required except on VDD.
GROUND DISCONNECT PROTECTION
In the event the 33874 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the state of the output at the time of
disconnection. A 10K Ω resistor needs to be added between
the wake pin and the rest of the circuitry in order to ensure
that the device turns off in case of ground disconnect and to
prevent this pin to exceed its maximum ratings.
Current limit resistors in the digital input lines protect the
digital supply against excessive current (10k Ω typical).
low as -16V. Under these conditions, the output’s gate is
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
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