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参数资料
| 型号： | MC33910G5AC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 43/90页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM BASIS CHIP 32LQFP |
| 标准包装： | 250 |
| 应用： | 系统基础芯片 |
| 电流 - 电源： | 4.5mA |
| 电源电压： | 5.5 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 托盘 |
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MC33910G5AC/MC3433910G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Table 23. Cyclic Sense and Force Wake-up Interval
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
CYSX8 (66)
X
0
0
0
0
0
0
0
1
1
1
1
1
CYST2
0
0
0
0
1
1
1
1
0
0
0
1
1
CYST1
0
0
1
1
0
0
1
1
0
1
1
0
0
CYST0
0
1
0
1
0
1
0
1
1
0
1
0
1
Interval
No cyclic sense (67)
20 ms
40 ms
60 ms
80 ms
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
software debugging and for programming the Flash memory.
1 = Watchdog is disabled
0 = Watchdog is enabled
WDWO - Watchdog Window Open
This read-only bit signals when the watchdog window is
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
1 = Watchdog window open
0 = Watchdog window closed
Analog Multiplexer Control Register - MUXCR
This register controls the analog multiplexer and selects
the divider ration for the L1 input divider.
Table 25. Analog Multiplexer Control Register -$C
1
1
1
0
960 ms
C3
C2
C1
C0
1
1
1
1
1120 ms
Write
L1DS
MX2
MX1
MX0
Notes
66. bit CYSX8 is located in Configuration Register (CFR)
67. No Cyclic Sense and no Force Wake-up available.
Reset
Value
1
0
0
0
Watchdog Status Register - WDSR
Reset
Condition
POR
POR, Reset mode or ext_reset
This register returns the Watchdog status information and
is also returned when writing to the TIMCR.
Table 24. Watchdog Status Register - $A/$B
L1DS - L1 Analog Input Divider Select
This write-only bit selects the resistor divider for the L1
analog input. Voltage is internally clamped to VDD.
S3
S2
S1
S0
0 = L1 Analog divider: 1
Read
WDTO
WDERR
WDOFF
WDWO
1 = L1 Analog divider: 3.6 (typ.)
WDTO - Watchdog Timeout
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
Any access to this register or the Timing Control Register
(TIMCR) will clear the WDTO bit.
1 = Last reset caused by watchdog timeout
MXx - Analog Multiplexer Input Select
These write-only bits selects which analog input is
When disabled or when in Stop or Sleep mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Table 26. Analog Multiplexer Channel Select
0 = None
WDERR - Watchdog Error
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The Windowing function is
disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
WDOFF - Watchdog Off
MX2
0
0
0
0
1
1
1
1
MX1
0
0
1
1
0
0
1
1
MX0
0
1
0
1
0
1
0
1
Meaning
Disabled
Reserved
Die Temperature Sensor
VSENSE input
L1 input
Reserved
Reserved
Reserved
This read-only bit signals that the watchdog pin connected
to Ground and therefore disabled. In this case watchdog
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
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| MC33910G5ACR2 | 功能描述:LIN 收发器 SBC LIN 2.5G Low end RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
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| MC33911G5AC | 功能描述:LIN 收发器 SBC LIN 2.5G Medium end RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
| MC33911G5ACR2 | 功能描述:LIN 收发器 SBC LIN 2.5G Medium end RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
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