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| 型号： | MC33910G5AC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 44/90页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM BASIS CHIP 32LQFP |
| 标准包装： | 250 |
| 应用： | 系统基础芯片 |
| 电流 - 电源： | 4.5mA |
| 电源电压： | 5.5 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 托盘 |
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MC33910G5AC/MC3433910G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Configuration Register - CFR
This register controls the Hall Sensor Supply enable/
disable and the cyclic sense timing multiplier.
Table 27. Configuration Register - $D
HSM - High Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the high side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
C3
C2
C1
C0
LINM - LIN Interrupts Mask
Write
Reset
Value
Reset
Condition
HVDD
0
POR, Reset
mode or
ext_reset
CYSX8
0
POR
0
0
POR
0
0
POR
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
HVDD - Hall Sensor Supply Enable
This write-only bit enables/disables the state of the hall
sensor supply.
1 = HVDD on
0 = HVDD off
CYSX8 - Cyclic Sense Timing x 8.
This write-only bit influences the cyclic sense and Forced
1 = Multiplier enabled
0 = None
Interrupt Mask Register - IMR
This register allows masking of some of the interrupt
sources. No interrupt will be generated to the MCU and no
flag will be set in the ISR register. The 5.0V Regulator over-
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the V SUP over-voltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled
Interrupt Source Register - ISR
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10μs and
then be driven low again.
This register is also returned when writing to the Interrupt
Mask Register (IMR).
Table 29. Interrupt Source Register - $E/$F
temperature prewarning interrupt and Under-voltage (VSUV)
interrupts can not be masked and will always cause an
S3
S2
S1
S0
interrupt.
Read
ISR3
ISR2
ISR1
ISR0
Writing to the IMR will return the ISR.
ISRx - Interrupt Source Register
Table 28. Interrupt Mask Register - $E
These read-only bits indicate the interrupt source following
C3
C2
C1
C0
Write
Reset
Value
HSM
1
0
1
LINM
1
VMM
1
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
Reset
Condition
POR
33910
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
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| MC33910G5ACR2 | 功能描述:LIN 收发器 SBC LIN 2.5G Low end RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
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| MC33911BACR2 | 功能描述:LIN 收发器 SBC LIN2G MEDIUM END RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
| MC33911G5AC | 功能描述:LIN 收发器 SBC LIN 2.5G Medium end RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
| MC33911G5ACR2 | 功能描述:LIN 收发器 SBC LIN 2.5G Medium end RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
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