参数资料
| 型号： | MC34703PNB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 19/46页 |
| 文件大小： | 0K |
| 描述： | IC POWER SUPPLY QUICC 33-QFN |
| 标准包装： | 1 |
| 应用： | 电源 |
| 电流 - 电源： | 60mA |
| 电源电压： | 2.8 V ~ 13.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 33-PowerQFN |
| 供应商设备封装： | 33-PQFN（10x10） |
| 包装： | 管件 |
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
timer expires after 100 ms, the LDO tries to power up again
for 10 ms, repeatedly checking for the overcurrent condition.
The current limit of the LDO is determined by the
following formula:
I LIM = 45 mV / R S
Where R S is the LDO current sense resistor, connected
between the ISNS pin and the LDO pin output (see
The output voltage of the LDO can be adjusted by means
of an external resistor divider connected to the feedback
control pin LFB. The linear regulator output voltage can be
adjusted in the range of 0.8 V to 5.0 V, but the LDO output
voltage is always lower than the input voltage to the regulator.
Power-up, power-down, and fault management are
coordinated with the switching regulator.
THERMAL SHUTDOWN
In order to increase the overall safety of the system
designed with the 34703, an internal thermal shutdown
Figure 15. LDO Converter Overcurrent Protection
SWITCHING OSCILLATOR
A 300 kHz (default) oscillator sets the switching frequency
of the buck regulator. The frequency of the oscillator can be
adjusted between 200 kHz and 400 kHz by an optional
external resistor R F connected from the FREQ pin of the
integrated circuit to ground. See Figure 10 for frequency
resistor selection.
The CLKSYN pin can be configured either as an oscillator
output when the CLKSEL pin is left open or it can be used as
a synchronization input when the CLKSEL pin is grounded.
The oscillator output signal is a square wave logic signal with
50 percent duty cycle, 180 degrees out-of-phase with the
internal clock signal. This allows opposite phase
synchronization of two 3370x devices.
When the CLKSYN pin is used as synchronization input
(CLKSEL pin grounded), the external resistor R F chosen from
the chart in Figure 10 should be used to synchronize the
internal ramp generator to the external clock. Operation is
only recommended between 200 kHz and 400 kHz. The
supplied synchronization signal does not need to be
50 percent duty cycle. Minimum pulse width is 300 ns.
LOW DROPOUT LINEAR REGULATOR (LDO)
The adjustable low dropout linear regulator (LDO) is
capable of supplying up to a 2.0 A output current. It has a
current limit feature with retry capability.
Current limiting is implemented via a sense resistor that
feeds back a small voltage to the ISNS pin. When the sense
resistor is used, the control circuit limits the current for 10 ms
when the voltage measured across the current sense resistor
reaches a 45 mV threshold. If the overcurrent condition still
exists after the 10ms time period, the linear regulator is
turned off. At the same time the overcurrent condition is
detected, the Retry Timer starts to count down. When the
function has been incorporated into the switching regulator
circuit. The 34703 senses the temperature of the buck
regulator main switching FET (high-side FET Q1; see
circuit. If the temperature of any of the monitored components
exceeds the limit of safe operation (thermal shutdown), the
switching regulator will be shut down. After the temperature
falls below the value given by the thermal shutdown
hysteresis window, the switcher will retry to operate again.
The V OUT /LDO pull-down FETs Q3/Q4 have an
independent thermal shutdown control. When the Q3/Q4
temperature exceeds the thermal shutdown limit, Q3/Q4 will
be turned off without affecting the switcher operation.
The maximum junction temperature is 125 ° C and thermal
shutdown is 170 ° C. It is not recommended to operate this IC
beyond these thresholds.
WATCHDOG TIMER
A watchdog function is available via I 2 C bus
communication. It is possible to select either window
watchdog or time-out watchdog operation, as illustrated in
Watchdog time-out starts when the watchdog function is
activated via I 2 C bus sending a Watchdog Programming
command byte, thus determining watchdog operation
(window or time-out) and period duration (refer to Table 6 ). If
the watchdog is cleared by receiving a new Watchdog
Programming command through the I 2 C bus, the watchdog
timer is reset and the new t ime-ou t period begins. If the
watchdog time expires, the RESET will become active (LOW)
for a time determined by the RC components of the RT timer
plus 10 ms. After a watchdog time-out, the function is no
longer active.
When the Window Watchdog function is selected, the
timer cannot be cleared during the Closed Window time,
which is 50% of the total watchdog period. When the
watchdog is cleared, the timer is reset and starts a new time-
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
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