参数资料
| 型号： | MC34703PNB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 23/46页 |
| 文件大小： | 0K |
| 描述： | IC POWER SUPPLY QUICC 33-QFN |
| 标准包装： | 1 |
| 应用： | 电源 |
| 电流 - 电源： | 60mA |
| 电源电压： | 2.8 V ~ 13.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 33-PowerQFN |
| 供应商设备封装： | 33-PQFN（10x10） |
| 包装： | 管件 |
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
6. LDO > V OUT , reset (4) and (5) above. Normal operation
resumes when LDO > V OUT .
Inverted Power Sequencing Control
Comparators monitor voltage differences between the
switcher (V OUT pin) and LDO (LDO pin) outputs as follows:
1. V OUT > LDO + 2.2 V, turn off V OUT . The switcher V OUT
can be forced off. This occurs whenever the V OUT
output voltage exceeds the LDO output voltage by
more than 2.3 V.
2. V OUT > LDO + 2.4 V, shunt V OUT to ground. If turning
off the switcher V OUT is insufficient and the V OUT
output voltage exceeds the LDO output voltage by
more than 2.4 V, a 1.0 ? shunt FET is turned on that
discharges the V OUT load capacitor to ground. The
shunt FET is used for LDO output shorts to ground and
for power-down in case of V IN1 ≠ V IN2 with LDO output
falling faster than the V OUT .
3. V OUT < LDO + 2.2 V, cancel (1) and (2) above, re-
enable V OUT . Normal operation resumes when the
V OUT output voltage is less than 2.2 V above the LDO
output voltage.
4. V OUT < LDO - 0.2 V, turn off LDO. The LDO can be
forced off. This occurs whenever the V OUT is less than
V LDO - 0.2 V.
5. V OUT < LDO - 0.3 V, turn on the 1.0 ? LDO sink FET.
This occurs when the LDO output voltage exceeds the
V OUT output by more than 300 mV.
6. V OUT > LDO, reset (4) and (5) above. Normal operation
resumes when V OUT > LDO.
STANDARD OPERATING MODE
Single 3.3 V Supply, V IN = V IN1 = V IN2 = 3.3 V
The 3.3 V supplies the microprocessor I/O voltage, the
switcher supplies core voltage (e.g., 1.8 V nominal), and the
LDO operates independently (see Figure 17 , page 21 ).
Power sequencing depends only on the normal switcher
intrinsic operation to control the Buck High-Side FET.
Power Up
When V IN is rising, initially V OUT will be below the
regulation point and the Buck High-Side FET will be on. In
order not to exceed the 2.5 V differential requirement
between the I/O (V IN ) and the core (V OUT ), the switcher must
start up at 2.5 V or less and be able to maintain the 2.5 V or
less differential. The maximum slew rate for V IN is 1.0 V/ms.
Power Down
When V IN is falling, V OUT will be below the regulation point;
therefore the Buck High-Side FET will be on. In the case
where V OUT is falling faster than V IN , the Buck High-Side FET
will attempt to maintain V OUT . In the case where V IN is falling
faster than V OUT , the Buck High-Side FET is also on, and the
V OUT load capacitor will be discharged through the Buck
High-Side FET to V IN . Thus, provided V IN does not fall too
fast, the core voltage (V OUT ) will not exceed the I/O voltage
(V IN ) by more than a maximum of 0.4 V.
Shorted Load
1. V OUT shorted to ground. This will cause the I/O voltage
to exceed the core voltage by more than 2.5 V. The
load is protected by a current limit.
2. V IN shorted to ground. Until the switcher load
capacitance is discharged, the core voltage will exceed
the I/O voltage by more than 0.4 V. By the intrinsic
operation of the switcher, the load capacitor will be
discharged rapidly through the Buck High-Side FET to
V IN .
3. V OUT shorted to supply. No load protection. 34703
protected by a thermal limit.
Single 5.0 V Supply, V IN1 = V IN2 , or Dual Supply
V IN1 ≠ V IN2
The LDO supplies the microprocessor I/O voltage. The
switcher supplies the core (e.g., 1.8 V nominal) (see
Power Up
This condition depends upon the regulator current limit,
load current and capacitance, and the relative rise times of
the V IN1 and V IN2 supplies. There are 2 cases:
1. LDO rises faster than V OUT . The LDO uses control
methods (1) and (2) described in the Methods of
Control section, page 22 .
2. V OUT rises faster than LDO. The switcher uses control
methods (4) and (5) described in the Methods of
Control section.
Power Down
This condition depends upon the regulator load current
and capacitance and the relative fall times of the V IN1 and
V IN2 supplies. There are 2 cases:
1. V OUT falls faster than LDO. The LDO uses control
methods (1) and (2) described in the Methods of
Control section, page 22 .
In the case V IN1 = V IN2 the intrinsic operation will turn on
both the Buck High-Side FET and the LDO external Pass
FET, and will discharge the LDO load capacitor into the
V IN supply.
2. LDO falls faster than V OUT . The switcher uses control
methods (4) and (5) described in the Methods of
Control section.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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