参数资料
| 型号： | MC34703PNB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 22/46页 |
| 文件大小： | 0K |
| 描述： | IC POWER SUPPLY QUICC 33-QFN |
| 标准包装： | 1 |
| 应用： | 电源 |
| 电流 - 电源： | 60mA |
| 电源电压： | 2.8 V ~ 13.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 33-PowerQFN |
| 供应商设备封装： | 33-PQFN（10x10） |
| 包装： | 管件 |
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POWER SEQUENCING
5.0 Vinput
34703
Requirements
VIN2
VBST
VIN1
LDRV
1. I/O supply voltage not to exceed core voltage by more
than 2.5 V.
VBST (sense)
VBD
ISNS
LDO
L C MP
3.3 V
VDDH (I/O)
2. Core supply voltage not to exceed I/O voltage by more
than 0.4 V.
FREQ
C LKSYN
SR
LFB
MCU
Methods of Control
5.0 V
SDA
S C L
EN1
EN2
RESET
BOOT
SW_A
SW_B
VBST
1.5 V
POR
VDDL ( C ore)
The 34703 has several methods of monitoring and
controlling the regulator output voltages, as described in the
paragraphs below. Power sequencing control is also
Optional
C LKSEL
ADDR
VDDI
VOUT
C OMP
INV
RT
achieved through the intrinsic operation of the regulators.
The EN1 and EN2 pins can be used to disable the power
sequencing (refer to Table 5 , page 15 ).
Intrinsic Operation
? V = 2.5 V
Max. Lead
V Start-Up
5.0 V Input Supply
3.3 V I/O Voltage (V LDO )
1.8 V Core Voltage
(V OUT )
? V = 2.5 V
Max. Lead
For both the LDO and switcher, whenever the output
voltage is below the regulation point, the LDO external Pass
FET will be on or the Buck High-Side FET will be on at a duty
cycle controlled by the switcher. Because these devices are
FETs, current can flow in either direction, balancing the
? V = 0.4 V
Max. Lag
? V = 0.4 V
Max. Lag
voltages via the common supply pin. The ability to maintain
the FETs on will depend on the available gate voltage, and
thus the size of the boost regulator storage capacitor.
Figure 18. Standard Power Up / Down Sequence
in +5.0 V Supply System
5.0 Vinput
Standard Power Sequencing Control
Comparators monitor voltage differences between the
LDO (LDO pin) and the switcher (V OUT pin) outputs as
follows:
VIN2
VBST
VBST (sense)
VBD
FREQ
C LKSYN
SDA
34703
VIN1
LDRV
ISNS
LDO
L C MP
SR
LFB
RESET
1.5 V
VDDL ( C ore)
MCU
POR
1. LDO > V OUT + 2.3 V, turn off LDO. The LDO can be
forced off. This occurs whenever the LDO output
voltage exceeds the switcher output voltage by more
than 2.3 V.
2. LDO > V OUT + 2.4 V, shunt LDO to ground. If turning
off the LDO is insufficient and the LDO output voltage
exceeds the switcher output voltage by more than
5.0 V
Optional
S C L
EN1
EN2
C LKSEL
ADDR
VDDI
BOOT
SW_A
SW_B
VOUT
C OMP
INV
RT
VBST
3.3 V
VDDH (I/O)
2.4 V, a 1.0 ? shunt FET is turned on that discharges
the LDO load capacitor to ground. The shunt FET is
used for switcher output shorts to ground and for power
down in case of V IN1 ≠ V IN2 with the switcher output
falling faster than the LDO.
3. LDO < V OUT + 2.2 V, cancel (1) and (2) above, re-
enable LDO. Normal operation resumes when the LDO
? V = 2.5 V
Max. Lead
V Start-Up
5.0 V Input Supply
3.3 V I/O Voltage (V OUT )
1.8 V Core Voltage (V LDO )
? V = 0.4 V
? V = 0.4 V
Max. Lag
Max. Lag
? V = 2.5 V
Max. Lead
output voltage is less than 2.2 V above the switcher
output voltage.
4. LDO < V OUT - 0.1 V, turn off switcher. The switcher can
be forced off. This occurs whenever the LDO is less
than V OUT - 0.1 V.
5. LDO < V OUT - 0.3 V, turn on Sync (LS) FET and 1.0 ?
V OUT sink FET. The Buck High-Side FET is forced off
Figure 19. Inverted Power Up / Down Sequence
in +5.0 V Supply System
and the Sync FET is forced on. This occurs when the
switcher output voltage exceeds the LDO output by
more than 300 mV.
34703
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
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