参数资料
型号: MC34703PNB
厂商: Freescale Semiconductor
文件页数: 25/46页
文件大小: 0K
描述: IC POWER SUPPLY QUICC 33-QFN
标准包装: 1
应用: 电源
电流 - 电源: 60mA
电源电压: 2.8 V ~ 13.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 33-PowerQFN
供应商设备封装: 33-PQFN(10x10)
包装: 管件
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
The 34703 device is compatible with the I C interface
I 2 C BUS OPERATION
2
standard. SDA and SCL pins are the Serial Data and Serial
Clock pins of the I 2 C bus.
I 2 C COMMAND AND DATA FORMATS
Writing Data Into the Slave Device
After the address acknowledgment by the slave, DATA
can be written into the slave registers. The R/W bit must be
set to 0 so DATA will be written. Figure 22 shows the data
write sequence. Actions performed by the slave device are
grayed.
Communication Start
Communication starts with a START condition, followed by
S
7-Bit Address
0
Ack
DATA
Ack
the slave device unique address. Figure 20 illustrates the
data transfer beginning an I 2 C communication for a 7-bit
slave address.
(W i )
Figure 22. Data Transfer for Write Operations
Data Definition
For the sake of the 34703 acting as a slave device, the
S
7-Bit Address
R/W
Ack
master writes a Command Byte and writes one Data Byte.
The Command Byte identifies the kind of operation required
Figure 20. Communication Using 7-Bit Address
Slave Address Definition
The 34703 has the two LSB’s address bits defined by the
state of the CLKSEL pin and the ADDR pin.
Note The state of the CLKSEL pin also defines the
by the master and has two fields, as illustrated in Figure 23 :
1. Address field
2. Value field
The address field is selected from the list in Table 8 .
configuration of the oscillator synchronization CLKSYN pin.
Bits
7
6
5
4
3
2
1
0
This feature allows up to four 34703 ICs to communicate
in the same I 2 C bus, all of them sharing the same high-order
D7 D6 D5 D4 D3 D2 D1 D0
address bits. A different combination of bits A1 and A0 is
assigned to each individual part to assure its unique address.
Address Field
Value Field
Figure 21 illustrates the flexible addressing feature for a 7-bit
address. Table 7 provides the definition of the selectable
portion of the device address.
Figure 23. Command Byte
Table 8. Address Field Definitions
Code
Operation
Write
Bits 6
5
4 3 2 1
0
001
Voltage Margining
W
1
1
1
0
1
A1 A0
010
Not Used
Fixed Address
Selectable
011
Watchdog
W
Address
Figure 21. Address Bit Definition for 7-Bit Address
Table 7. Definition of Selectable Portion of Device
Address
Refer to Table 10 , page 26 , which summarizes the value
field definitions for the entire set of operation options.
CLKSEL Pin
Low
Low
Open
Open
ADDR Pin
Low
Open
Low
Open
A1
0
0
1
1
A0
0
1
0
1
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
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