参数资料
型号: MC68307PU16
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
封装: TQFP-100
文件页数: 133/264页
文件大小: 949K
代理商: MC68307PU16
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Applications Information
MOTOROLA
MC68307 USER’S MANUAL
10-11
10.3.1 Overview of M-Bus Software Transfer Mechanism
For clarity, a brief overview of the M-bus software control mechanism is provided here.
The M-bus communication is on a byte-wide basis. The components of the hardware trans-
fer protocol are a START condition, 8 data bits, an acknowledge bit and a STOP condition.
Before starting a communication, an M-bus master should carry out a software check to
ensure the bus is free, and therefore all other M-bus transfers are complete. Thereafter, the
bus master initiates a transfer by software, writing a START condition onto the bus. This is
an indicator to all connected M-bus devices that the master is taking charge of the bus and
that the address of the targeted slave is to follow. For the MC68300 M-bus master, writing
the targeted slave address to the data register initiates the 8-bit transfer (MSB first).
If a system has two or more M-bus masters which poll the bus free and start a transfer at
the same time, then the collision detection arbitration throughout the transfer of the slave
address transfer and subsequent data bytes decides which device gets charge of the bus.
If the MC68300 M-bus loses arbitration in this way, it stops driving data onto the bus to pre-
vent data corruption. Furthermore, it switches automatically into slave mode, pre-empting
the alternate master addressing it as a slave. If interrupts are enabled, an interrupt is gen-
erated on the completion of that byte, and a status bit indicates arbitration lost as the inter-
rupt source.
The first data byte transmitted by the M-bus master is always the targeted slave address,
with the least significant bit determining whether the slave remains ready to receive or trans-
mit subsequent bytes. The addressed slave can then acknowledge the received byte, or not,
depending upon the software protocol and acknowledge capability of the slave devices
used. Each acknowledge is like a 9th data bit, asserted by the receiver as a handshake to
successfully transmitted data.
A block transfer comprising a series of data bytes (and acknowledge bits) follows as com-
manded by the software protocol. The bus remains busy throughout the block, precluding
all other masters from starting transfers. At the end of the block, the bus master relinquishes
the bus by software placing a STOP condition onto the bus.
Ultimately, the M-bus master is responsible for starting and stopping transfers, but the num-
ber of bytes transferred can be dictated by either the master or slave depending upon the
desired software protocol. For example, a slave may acknowledge all bytes received until it
saturates, at which point the master STOPs the block transfer. Alternatively, the slave
receiver may acknowledge received bytes until the master transmitter indiates that there are
no more bytes to send. Indeed, both master and slave can be charged with controlling the
transfer block. For instance, the software protocol may transfer a byte count as part of the
communication or use a fixed number of transfer bytes every time.
For the best choice in software control, transfers can adopt either a status polling method or
interrupts at the end of each byte. The interrupt option is most commonly used to minimize
the processor overhead or the time during which the processor is tied up with the transfers.
If enabled, the interrupts are generated on the completion of each 9 bits (8 data bits plus an
acknowledge).
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