System Integration Module
5-32
MC68307 USER’S MANUAL
MOTOROLA
EN—Enable
This bit enables or disables one of the chip select outputs and its associated DTACK gen-
erator. This bit can be set in the same write cycle as the setting of other fields.
0 = The chip select line is disabled.
1 = The chip select line is enabled.
After system reset, all chip selects are enabled, however only chip select 0 asserts due to
the priority mechanism. The chip select does not require disabling before changing its pa-
rameters, although care should be taken if altering the configuration of the chip select that
is currently asserting on the instruction stream, e.g., to relocate ROM to a higher address.
It is best to ensure that both base register and option register are written in one long word
cycle.
5.2.2.2 OPTION REGISTERS (OR3–OR0). These four 16-bit registers consist of a base
address mask field, a read/write mask bit, a compare function code bit, and a DTACK
generation field.
DTACK Field
These bits are used to determine whether DTACK is generated internally with a program-
mable number of wait states or externally by the peripheral. With internal DTACK gener-
ation, zero to six wait states can be automatically inserted before the DTACK pin is
Chip select 3 when used in the 8051-compatible bus mode, has a minimum of 6 and a
maximum of 12 wait-states. The meaning of the DTACK bits changes accordingly as
shown in the table.
OR0, OR1, OR2, OR3
MBASE+$042, $046, $04A, $04E
15
13
12
2
1
0
DTACK
Base Address Mask (M23–M13)
MRW
CFC
RESET:
1
0
1
0
1
Read/Write
Supervisor or User
Table 5-6. DTACK Field Encoding
Bits
M68000-Bus Cycles
Description
8051-Compatible Bus Cycles
Description
15
14
13
0
No Wait State
6 Wait States
0
1
1 Wait State
7 Wait States
0
1
0
2 Wait States
8 Wait States
0
1
3 Wait States
9 Wait States
1
0
4 Wait States
10 Wait States
1
0
1
5 Wait States
11 Wait States
1
0
6 Wait States
12 Wait States
1
External DTACK