Bus Operation
MOTOROLA
MC68307 USER’S MANUAL
3-33
increases performance by observing timing parameters related to the system clock fre-
quency without being completely synchronous with that clock. A memory array designed to
operate with a particular frequency processor but not driven by the processor clock is a com-
mon example of a pseudo-asynchronous device.
The designer of a fully asynchronous system can make no assumptions about address
setup time, which could be used to improve performance. With the system clock frequency
known, the slave device can be designed to decode the address bus before recognizing an
address strobe. Parameter #11 (refer to Section 11.7 AC Electrical Specifications—Read
and Write Cycles (VCC = 5.0V
± 0.5V or 3.3Vdc ± 0.3V; GND = 0Vdc; TA = TL to TH)
(see Figure 11-3 and Figure 11-4)) specifies the minimum time before address strobe dur-
ing which the address is valid.
In a pseudo-asynchronous system, timing specifications allow DTACK to be asserted for a
read cycle before the data from a slave device is valid. The length of time that DTACK may
precede data is specified as parameter #31. This parameter must be met to ensure the valid-
ity of the data latched into the processor. No maximum time is specified from the assertion
of AS to the assertion of DTACK. During this unlimited time, the processor inserts wait
cycles in one-clock-period increments until DTACK is recognized.
Figure 3-33 shows the
important timing parameters for a pseudo-asynchronous read cycle.
During a write cycle, after the processor asserts AS but before driving the data bus, the pro-
cessor drives R/W low. Parameter #55 specifies the minimum time between the transition
Figure 3-30. Fully Asynchronous Write Cycle
Figure 3-31. Fully Asynchronous Read Cycle
ADDR
AS
R/W
UDS/LDS
DATA
DTACK
ADDR
AS
R/W
UDS/LDS
DATA
DTACK
AS
R/W
DTACK
UDS/LDS
DATA
ADDR
AS
R/W
UDS/LDS
DATA
DTACK