
MOTOROLA
11-4
MC68HC05G1
LOW POWER MODES
11
11.2
Wait Mode
The WAIT instruction places the MC68HC05G1 in a low power consumption mode. In Wait mode,
all CPU activities are stopped, but the internal clock, programmable timer, serial peripheral
interface and real time clock remain active. Refer to
Figure 11-2 for Wait owchart. On entering
Wait mode, the I bit in the condition code register is cleared to enable all interrupts. In Wait mode
all registers and memory remain unaltered and all parallel input/output lines remain unchanged.
In additions to interrupts from IRQ, INT1, INT2, RTC, interrupts from either programmable timer,
or SPI will cause the processor to exit Wait mode. If a non-reset exit from Wait mode is performed
(e.g. timer overow interrupt exit), the system will continue from the state before it entered Wait
mode. If a reset exit from Wait mode is performed all the systems revert to the disabled reset state.
In Wait mode, device power consumption depends on how many systems are active. The power
consumption will be the lowest when the SPI and the Timer are disabled (the RTC cannot be
disabled in Wait mode).
11.2.1
Programmable during Timer Wait Mode
The timer system is not affected by the Wait mode and continues regular operation. Any valid timer
interrupt will wake the system up.
11.2.2
RTC during Wait Mode
The RTC system is not affected by the Wait mode and continues regular operation. Any valid RTC
interrupt will wake the system up.
11.2.3
SPI during Wait Mode
The SPI system is not affected by the Wait mode and continues regular operation. Any valid SPI
interrupt will wake the system up. See also Section 8.5.
11.3
Data Retention Modes
The contents of RAM and CPU registers are retained at supply voltages as low as 2.0 Vdc. This
is referred to as the data retention mode, where the data is held, but the device is not guaranteed
to operate.
TPG
98