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参数资料
| 型号： | MC68HC05G1B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | SDIP-56 |
| 文件页数： | 98/124页 |
| 文件大小： | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
8-9
SERIAL PERIPHERAL INTERFACE
8
8.4.1.4
CPOL - Clock Polarity
1 (set)
–
SCK pin high during master idle
0 (clear) –
SCK pin low during master idle
The clock polarity bit controls the normal or steady state logic of the clock when data is not being
transferred. The CPOL bit affects both the master and slave modes. It must be used in conjunction
with the clock phase control bit (CPHA) to produce the desired clock-data relationship between a
master and a slave device. When the CPOL bit is a logic zero, it produces a steady state low value
at the SCK pin of the master device. If the CPOL bit is a logic one, a high value is produced at the
SCK pin of the master device when data is not being transferred. The CPOL bit is not affected by
reset. Refer to Figure 8-2.
8.4.1.5
CPHA - Clock Phase
1 (set)
–
2nd clock edge transition
0 (clear) –
1st clock edge transition
The clock phase bit controls the relationship between the data on the MISO and MOSI pins and
the clock produced or received at the SCK pin. This control has effect in both the master and slave
modes. It must be used in conjunction with the clock polarity control bit (CPOL) to produce the
wanted clock-data relation. The CPHA bit in general selects the clock edge which captures data
and allows it to change states. It has its greatest impact on the rst bit transmitted (MSB) in that it
does or does not allow a clock transition before the rst data capture edge. The CPHA bit is not
affected by reset. Refer to Figure 8-2.
8.4.1.6
SPR1, SPR0 - Serial Peripheral Rate
These two serial peripheral rate bits select one of four baud rates to be used as SCK if the device
is a master; however, they have no effect in slave mode. The slave device is capable of shifting
data in and out at a maximum rate which is equal to the CPU clock. A rate table is given below for
the generation of the SCK from the master. The SPR1 and SPR0 bits are not affected by reset.
SPR1
SPR0
INTERNAL PROCESSOR CLOCK
DIVIDE BY
00
2
01
4
10
16
11
32
TPG
71
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