参数资料
型号: MC68HC05G1B
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封装: SDIP-56
文件页数: 91/124页
文件大小: 732K
代理商: MC68HC05G1B
MC68HC05G1
MOTOROLA
8-3
SERIAL PERIPHERAL INTERFACE
8
8.2
SPI Signals Description
The four basic SPI signals (MOSI, MISO, SCK, and SS) are described in the following paragraphs.
Each signal is described for both the master and slave mode.
8.2.1
Master Out Slave In (MOSI)
The MOSI pin is congured as an output in a master (mode) device and as an input in a slave
(mode) device. Data is transferred serially from a master to a slave on this line, most signicant
bit rst. The timing diagram of Figure 8-2 shows the relationship between data and serial clock
(SCK). As shown in Figure 8-2, four possible timing relationships may be chosen by using control
bits CPOL and CPHA. The master device always allows data to be applied on the MOSI line a
half-cycle before the serial clock edge (SCK) in order for the slave device to latch the data.
Figure 8-2 SPI Data/Clock Timing Diagram
(CPOL=0, CPHA=0)
(CPOL=0, CPHA=1)
(CPOL=1, CPHA=0)
(CPOL=1, CPHA=1)
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
SS
SCK
MISO/MOSI
TPG
65
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