参数资料
型号: MC68HC05SB7
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封装: MO-150, SSOP-28
文件页数: 167/170页
文件大小: 2161K
代理商: MC68HC05SB7
GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
CURRENT SENSE AMPLIFIER
MC68HC05SB7
13-4
REV 2.1
CDIF — Current Detect Interrupt Flag
This read-only bit is set when the voltage developed across the sense resistor,
RSENSE is equal to or greater than VDET (the CSA comparator trip voltage,
typically –15mV) CDIF generates an interrupt request to the CPU if CDIE is
also set. The CDIF bit is cleared by writing a logic “1” to the CDIFR bit. Writing
to CDIF has no effect. Reset clears CDIF.
1 =
Current detect interrupt has occurred.
0 =
No current detect interrupt since CDIF last cleared.
If the OSC1 and OSC2 pins are not enabled (by mask option). The current detect
interrupt from CDIF bit can be reected to one of two output port pins, PB2/CS0
and PB3/CS1.
CSSEL — Current Sense detect output Select
This read/write bit selects either CS0 pin or CS1 pin is used to reect the cur-
rent detect interrupt. Reset clears the CSSEL bit.
1 =
CS1 enabled, CS0 disabled.
0 =
CS0 enabled, CS1 disabled.
Table 13-3. Current Detect Output Select
CS0 and CS1 are not available when OSC1 and OSC2 are used for external oscil-
lator option.
13.4
CSA OPERATION DURING WAIT MODE
In WAIT mode the CSA module continues to operate and may generate an inter-
rupt to trigger the MCU out of WAIT mode.
13.5
CSA OPERATION DURING STOP MODE
In STOP mode the CSA module is disabled; but a CSA interrupt (by CDIF) can
wake-up the MCU from the STOP mode.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MCR
R
TSEN
LVRON
0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
$000B
W
COPON
reset:
01000000
U = UNAFFECTED BY RESET
Figure 13-3. Miscellaneous Control Register (MCR)
CDEN
CSSEL
PB2/CS0
PB3/CS1
0
PB2
PB3
0
1
PB2
PB3
1
0
CS0
PB3
1
PB2
CS1
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