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参数资料
型号： MC68HC05SB7
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封装： MO-150, SSOP-28
文件页数： 56/170页
文件大小： 2161K
代理商： MC68HC05SB7
August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
INSTRUCTION SET
MOTOROLA
REV 2.1
17-13
SUB #
opr
SUB
opr
SUB
opr
SUB
opr,X
SUB
opr,X
SUB ,X
Subtract Memory
Byte from
Accumulator
A
← (A) – (M)
— — ¤¤¤
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SWI
Software Interrupt
PC
← (PC) + 1; Push (PCL)
SP
← (SP) – 1; Push (PCH)
SP
← (SP) – 1; Push (X)
SP
← (SP) – 1; Push (A)
SP
← (SP) – 1; Push (CCR)
SP
← (SP) – 1; I ← 1
PCH
← Interrupt Vector High Byte
PCL
← Interrupt Vector Low Byte
— 1 — — —
INH
83
10
TAX
Transfer
Accumulator to
Index Register
X
← (A)
—————
INH
97
2
TST
opr
TSTA
TSTX
TST
opr,X
TST ,X
Test Memory Byte
for Negative or Zero
(M) – $00
— — ¤¤ —
DIR
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
5
4
TXA
Transfer Index
Register to
Accumulator
A
← (X)
—————
INH
9F
2
WAIT
Stop CPU Clock and
Enable
Interrupts
— 0 — — —
INH
8F
2
A
Accumulator
opr
Operand (one or two bytes)
C
Carry/borrow flag
PC
Program counter
CCR
Condition code register
PCH
Program counter high byte
dd
Direct address of operand
PCL
Program counter low byte
dd rr
Direct address of operand and relative offset of branch instruction
REL
Relative addressing mode
DIR
Direct addressing mode
rel
Relative program counter offset byte
ee ff
High and low bytes of offset in indexed, 16-bit offset addressing
rr
Relative program counter offset byte
EXT
Extended addressing mode
SP
Stack pointer
ff
Offset byte in indexed, 8-bit offset addressing
X
Index register
H
Half-carry flag
Z
Zero flag
hh ll
High and low bytes of operand address in extended addressing
#
Immediate value
I
Interrupt mask
∧
Logical AND
ii
Immediate operand byte
∨
Logical OR
IMM
Immediate addressing mode
⊕
Logical EXCLUSIVE OR
INH
Inherent addressing mode
( )
Contents of
IX
Indexed, no offset addressing mode
–( )
Negation (two’s complement)
IX1
Indexed, 8-bit offset addressing mode
←
Loaded with
IX2
Indexed, 16-bit offset addressing mode
?
If
M
Memory location
:
Concatenated with
N
Negative flag
¤
Set or cleared
n
Any bit
—
Not affected
Table 17-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
H I NZC
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