August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
ANALOG SUBSYSTEM
MOTOROLA
REV 2.1
15-5
not be changed while waiting for a comparator ag. Further, any changes to the
state of the INV bit should be followed by writing a logical one to CPFR bit to clear
an extraneous CPF ag that may have occurred.
VREF
This is a read/write bit that connects the channel select bus to VDD for purposes
of making a reference voltage measurement. It cannot be selected if any of the
other input sources to the channel select bus are selected as shown in
Table 15-2. This bit is cleared by a reset of the device.
1 =
Channel select bus connected to VDD if MUX7:0 and IBREF are
cleared.
0 =
Channel select bus cannot be connected to VDD.
IBREF
This is a read/write bit that connects the channel select bus to VIB for purposes
of making a reference voltage measurement. It cannot be selected if any of the
other input sources to the channel select bus are selected as shown in
Table 15-2. This bit is cleared by a reset of the device.
1 =
Channel select bus connected to VIB if MUX7:0 and VREF are
cleared.
0 =
Channel select bus cannot be connected to VIB.
MUX7:0
These are read/write bits that connect the analog subsystem pins to the chan-
nel select bus and voltage comparator for purposes of making a voltage mea-
surement. They can be selected individually or combined with any of the other
input sources to the channel select bus as shown in Table 15-2.
NOTE
The VAOFF voltage source shown in Figure 15-1 depicts a small offset voltage generated by the total chip current passing through the package bond wires and
lead frame that are attached to the single VSS pin. The offset raises the internal
VSS reference (AVSS) in the analog subsystem with respect to the external VSS
pin. Turning on the VSS MUX to the channel select bus connects it to this internal
AVSS reference line.
When making A/D conversions this AVSS offset gets placed on the external
ramping capacitor since the discharge device on the CAP pin discharges the
external capacitor to the internal AVSS line. Under these circumstances the
positive input (+) to the comparator will always be higher than the negative input (–
) until the negative input reaches the AVSS offset voltage plus any offset in the
comparator.
Therefore, input voltages cannot be resolved if they are less than the sum of the
AVSS offset and the comparator offset, because they will always yield a low output
from the comparator