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| 型号： | MC68HC05T16B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | PLASTIC, SDIP-56 |
| 文件页数： | 49/128页 |
| 文件大小： | 734K |
| 代理商： | MC68HC05T16B |
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MC68HC05T16
MOTOROLA
3-1
MEMORY AND REGISTERS
3
MEMORY AND REGISTERS
This section describes the organization of the on-chip memory.
3.1
Memory Map
The CPU can address 64K-bytes of memory space. The ROM portion of memory holds the
program instructions, xed data, user-dened vectors, and interrupt service routines. The RAM
portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can
access their locations in the same way that it accesses all other memory locations. Figure 3-1
shows the Memory Map for the MC68HC05T16/
MC68HC705T16.
3.2
Input/Output Section
The rst 64 addresses of memory space, $0000-$003F, are the I/O section. These are the
addresses of the I/O control registers, status registers, and data registers. Table 3-1 shows these
registers and their respective bits.
3.3
RAM
The 320 addresses from $0050-$018F are RAM locations. The CPU uses the 64 RAM addresses,
$00C0-$00FF, as the stack. Before processing an interrupt, the CPU uses ve bytes of the stack
to save the contents of the CPU registers. During a subroutine call, the CPU uses two bytes of the
stack to store the return address. The stack pointer decrements during pushes and increments
during pulls.
Note:
Be careful when using nested subroutines or multiple interrupt levels. The CPU may
overwrite data in the RAM during a subroutine or during the interrupt stacking
operation. Once the stack pointer passes $00C0, it wraps round back to $00FF.
TPG
25
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