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参数资料
| 型号： | MC68HC05T16B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | PLASTIC, SDIP-56 |
| 文件页数： | 71/128页 |
| 文件大小： | 734K |
| 代理商： | MC68HC05T16B |
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MC68HC05T16
MOTOROLA
5-5
TIMERS
5
contains the free-running counter value that corresponds to the most recent input capture.After a
read of the input capture register MSB ($12), the counter transfer is inhibited until the LSB ($13)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period. A read of the input
capture register LSB ($13) does not inhibit the free-running counter transfer since they occur on
opposite edges of the internal bus clock.
5.1.4
Timer Control Register (TCR)
The TCR is a read/write register containing ve control bits. Four bits control interrupts associated
with each of the four ag bits found in the Timer Status register. The other bit controls which edge
is signicant to the input capture edge detector. The Timer Control register and the free-running
counter are the only sections of the timer affected by reset.
Denition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
1 (set)
–
Input Capture interrupt enabled.
0 (clear) –
Input Capture interrupt disabled.
OC0IE - Output Compare Interrupt Enable
1 (set)
–
Output Compare 0 interrupt enabled.
0 (clear) –
Output Compare 0 interrupt disabled.
OC1IE - Output Compare Interrupt Enable
1 (set)
–
Output Compare 1 interrupt enabled.
0 (clear) –
Output Compare 1 interrupt disabled.
TOVFIE - Timer Overow Interrupt Enable
1 (set)
–
Timer Overow interrupt enabled.
0 (clear) –
Timer Overow interrupt disabled.
IEDG - Input Edge
1 (set)
–
TCAP is positive-going edge sensitive.
0 (clear) –
TCAP is negative-going edge sensitive.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$10
ICIE
OC0IE
OC1IE
TOVFIE
IEDG
0000 0000
TPG
45
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