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参数资料
| 型号： | MC68HC05T16B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | PLASTIC, SDIP-56 |
| 文件页数： | 55/128页 |
| 文件大小： | 734K |
| 代理商： | MC68HC05T16B |
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MOTOROLA
4-2
MC68HC05T16
RESETS AND INTERRUPTS
4
4.1.3
Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specic amount of time by a program reset sequence.
Note:
COP time-out is prevented by periodically writing a ‘0’ to bit 0 of address $FFF0.
If the watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode it was in when the COP time-out was generated.
The watchdog timer is initially disabled after a reset, it is enabled by setting the WDOG bit in the
Multi-Function Timer register (writing a ‘1’ to bit 2 of address $1C); see Section 5.2 for more
details. Once enabled, it cannot be disabled by software.
Table 4-1 shows the internal circuit actions on reset, but not necessary in order of occurrence.
Table 4-1 Reset Action on Internal Circuit
DEFAULT CONDITIONS AFTER RESET
1
Timer prescaler reset to zero state
2
Timer counter congures to $FFFC
3
All timer interrupt enable bits cleared (ICIE, OC0IE, OC1IE, and TOVFIE) to disable timer interrupt
4
All data direction registers cleared to zero (default to inputs)
5
Port E and port F congured as general purpose I/O ports
6
Congure stack pointer to $00FF
7
Force internal address bus to the address of reset vector ($FFFE)
8
Set interrupt mask bit (I bit) in condition code register to logic one
9
Clear Stop latch
10
Clear Wait latch
11
Clear all interrupt enable bits
12
COP watchdog timer reset
13
COP watchdog disabled
14
Initialize M-Bus registers
15
Initialize PWM registers
16
Initialize PAC registers
17
OSD disabled, all registers initialized to default values
Listed numbers do not represent order of occurrence.
TPG
30
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