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参数资料
| 型号： | MC68HC05T16B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | PLASTIC, SDIP-56 |
| 文件页数： | 57/128页 |
| 文件大小： | 734K |
| 代理商： | MC68HC05T16B |
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MOTOROLA
4-4
MC68HC05T16
RESETS AND INTERRUPTS
4
4.2
INTERRUPTS
The MC68HC05T16 is capable of handling eight types of interrupt, seven hardware and one
software. The interrupt mask bit (“I” bit in the Condition Code register), if set, masks all interrupts
except the software interrupt, SWI. Interrupts such as Timer, M-Bus, OSD, and MFT have several
ags which will cause the interrupt. Interrupt ags are found in “read only” status registers, while
their enables are in associated control registers. They are never mixed in the same register. If the
enable bit is “0”, it masks the interrupt from occurring but does not inhibit the ag from being set.
A reset clears all enable bits. The general sequence for clearing an interrupt is a software
sequence of reading the status register while the ag is set followed by a read or write of an
associated register. When any of these interrupts occur, and if enabled, normal processing is
suspended at the end of the current instruction execution. The state of the machine is pushed onto
the stack (see Figure 4-2 for stacking order) and the appropriate vector points to the starting
address of the interrupt service routine (see Table 4-2). Also, the interrupt mask bit in the condition
code register is set. This masks further interrupts. At the completion of the service routine, the
software normally contains an RTI instruction which, when executed, restores the machine state
and continues executing the interrupted program. Interrupt priority is based on interrupt vector
addresses. The higher the vector addresses, the higher the priority. For example, OSD interrupts
have a higher priority than IRQ, TIMER, M-BUS, PAC, and MFT interrupts; but lower priority than
SWI and RESET.
Note:
The interrupt mask bit (I bit) will be cleared if and only if the corresponding bit stored
on the stack is zero.
Figure 4-2 Interrupt Stacking Order
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
$00FD
$00FE
$00FF (TOP OF STACK)
UNSTACKING
1
2
3
4
5
4
3
2
1
STACKING
ORDER
TPG
32
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