参数资料
型号: MC68HC11C0FN3
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68
封装: PLASTIC, LCC-68
文件页数: 11/76页
文件大小: 394K
代理商: MC68HC11C0FN3
MC68HC11C0
MOTOROLA
MC68HC11C0TS/D
19
Figure 6 Memory Expansion and Program Chip Select Block Diagram
In the following example the user has constructed a system composed of the MC68HC11C0 MCU and
a single 256-Kbyte external memory device. Since the user wishes to access all locations in the external
memory, the 256-Kbyte expansion mode is chosen (MEM[1:0] = 1:1). The window in which the pages
of expanded memory will appear is programmed to be located at $6000–$AFFF (PGSADR = $60, PGE-
ADR = $B0). Note that this also defines the range of the program chip select. PGEN0 must be set in
order for CSPROG to drive the external pin. Since the expansion window has been defined as 20
Kbytes in length, the 256-Kbyte external memory will be divided into 20-Kbyte segments (twelve 20-
Kbyte pages and one 16-Kbyte page). The vector chip select has been programmed to begin at $D000.
If the CPU address falls within the vector chip select range the vector chip select (CSV) is activated and
XA[17:16] are forced high to ensure that the very top of the external memory is accessed. Refer to the
Memory Expansion Address Translation Example diagram.
In this example the user will access the 20-Kbyte block in the external memory starting at external ad-
dress $0A000. The following are the corresponding parameters involved in the translation:
Desired Starting Expansion Page Address — MA[17:10] = $0A0 = %00 1010 00
Desired Starting Window Address — PSA[15:10] = $60 = %0110 00
In general, the formula for the value required in MXHADR/MXLADR is:
XA[17:10] = MA[17:10] –PSA[15:10]
The equation for this example translation is:
XA[17:10] = $0A0 –$60
+
MXHADR
MXLADR
CPU ADDR[15:10]
CPU ADDR[9:0]
MEM1
MEM0
PGSADDR
PGEADDR
CSPROG
ADDR[17:10]
ADDR[9:0]
6
8
10
6
2
COMPARE
ADDR[15:10]
≥ PSA[15:10]
?
COMPARE
ADDR[15:10] < PEA[15:10]
?
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