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参数资料
| 型号： | MC68HC11C0FN3 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 21/76页 |
| 文件大小： | 394K |
| 代理商： | MC68HC11C0FN3 |
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MOTOROLA
MC68HC11C0
28
MC68HC11C0TS/D
The timer forces the I/O state to output for each port A line associated with an enabled output compare.
In these cases the data direction bits will not be changed, but have no effect on these lines. The DDRA
will revert to controlling data direction when the associated timer compare is disabled. Input captures
do not force the I/O state of the pin or the state of DDRA.
DDA[7:0] — Data Direction for Port A
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
After reset PD[5:0] are configured as high impedance inputs. PD[5:0] share functions with the SCI, SPI,
and two interrupt request lines (IRQ and XIRQ). The actual function performed by each pin depends on
bits in DIOCTL, SCI/SPI enable bits, and bits in the DDRD register. Refer to the tables located in the
DIOCTL register description.
Bits [7:6] — Not implemented
Always read zero
DDD[5:0] — Data Direction for Port D
0 = Input
1 = Output
PORTA — Port A Data
$0000
Bit 7
654321
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
IIIIIIII
Alt. Pin
Func.:
PAI
OC2
OC3
OC4
OC5/IC4
IC1
IC2
IC3
And/or:
OC1
—
DDRA — Data Direction Register for Port A
$0001
Bit 7
654321
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
RESET:
00000000
PORTD — Port D Data
$0008
Bit 7
654321
Bit 0
—
PD5
PD4
PD3
PD2
PD1
PD0
RESET:
0
IIIIII
Alt. Pin
Func.:
—
SS
SCK
SDO/
MOSI
SDI/
MISO
TxD
RxD
or:
—
IRQ
—
XIRQ
——
DDRD — Data Direction Register for Port D
$0009
Bit 7
654321
Bit 0
—
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
RESET:
00000000
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相关代理商/技术参数 |
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