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参数资料
| 型号： | MC68HC11C0FN3 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 22/76页 |
| 文件大小： | 394K |
| 代理商： | MC68HC11C0FN3 |
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MC68HC11C0
MOTOROLA
MC68HC11C0TS/D
29
Bits [7:6] — Not implemented
Always read zero.
DIO[5:2] — Port D I/O Control for Port D Bits [5:2]
Refer to the following tables for description.
Bit 1 — Not implemented
Always reads zero.
DIO0 — Port D I/O Control for Port D Bit 0
Refer to the following tables for description.
Notes:
1. If a pin is configured for general-purpose I/O, the DDRD bit controls the direction of data.
2. If a pin is configured as SS, the MSTR and DDRD bits are the output enable.
3. SPE is the SPI enable bit, MSTR is the master/slave select bit. Refer to the SPCR register.
4. IRQ or SS inputs are internally pulled high if not used. This does not affect the pin.
Notes:
1. If a pin is configured for general-purpose I/O, the DDRD bit controls the direction of data.
2. If a pin is configured as MOSI, the MSTR and DDRD bit control the direction of data.
3. SPE is the SPI enable bit, MSTR is the master/slave select bit. Refer to the SPCR register.
DIOCTL — Port D I/O Control
$0007
Bit 7
654321
Bit 0
—
DIO5
DIO4
DIO3
DIO2
—
DIO0
RESET:
00111100
Table 3 PD5 Configuration
SPI Enable
DIOCTL
Bit 5
DIOCTL
Bit 4
PD5
Pull-Up
Control
Output
Enable
SPE = 0
0
X
I/O
DDD5
1
0
IRQ
On
Off
1
I/O
DDD5
SPE = 1
0
X
I/O
DDD5
1
0
IRQ
On
Off
11
SS
Off
MSTR + DDD5
Table 4 PD[4:3] Configuration
SPI Enable
PD4
PD3
Pull-Up
Control
Output
Enable
SPE = 0
I/O
DDD[4:3]
SPE = 1
MOSI
SCK
Off
MSTR + DDD[4:3]
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