参数资料
型号: MC68MH360VR25L
厂商: Freescale Semiconductor
文件页数: 107/158页
文件大小: 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
标准包装: 44
系列: M683xx
处理器类型: M683xx 32-位
速度: 25MHz
电压: 5V
安装类型: 表面贴装
封装/外壳: 357-BBGA
供应商设备封装: 357-PBGA(25x25)
包装: 托盘
QMC Supplement
Table 2-11. CHAMR Bit Settings (Transparent Mode)
Field
Name
Description
0
MODE
Mode—Each channel has a programmable option whether to use transparent mode or HDLC
mode.
0 Transparent mode
1 HDLC mode
1
RD
Reverse data
0 The bit order will not be reversed, transmitting/receiving the LSB of each octet rst.
1 The bit order as seen on the channels is reversed, transmitting/receiving the MSB of each
octet rst.
2—
1
3
ENT
Enable transmit
0 Disable transmitter. If this bit is cleared and the channel’s transmitter is routed to a certain
time slot (within TSATTx, see Figure 2-3) the transmitter sends 1’s on this time slot.
1 The transmit portion of the channel is enabled and data is sent according to protocol and to
other control settings.
4
Reserved
5
SYNC
Synchronization—Controls synchronization of multichannel operation in transparent mode.
0 The rst byte is put in the rst available time slot or is read from the rst available time slot to
this logical channel.
1 The synchronization algorithm according to TRANSYNC is done.
6
RES
Reserved
7
POL
Enable polling—Enables the transmitter to poll the transmit BDs.
0 The CPM will not check the ready (R) bit in the transmit buffer descriptor.
1 The CPM will go check the ready (R) bit in the transmit buffer descriptor.
The user can use this bit to prevent unnecessary external bus cycles when checking the ready
bit (R) in the buffer descriptor. Software should always set POL at the beginning of a transmit
sequence of one or more frames. The RISC processor clears POL (0) when no more buffers are
ready in the transmit queue when it nds a buffer descriptor with the R bit cleared (0), that is, at
the end of a frame or at the end of a multiframe transmission. To prevent deadlock, software
should prepare the new BD, or multiple BDs, and set (1) the ready (R) bit in the BD before setting
(1) POL.
Note that the CPM automatically clears this bit; the user should never try to clear this bit in
software.
8–9
0
10–11
Reserved
12–15
0
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相关PDF资料
PDF描述
MC68MH360CVR25L IC MPU QUICC 25MHZ 357-PBGA
HMC40DTEI CONN EDGECARD 80POS .100 EYELET
FMC50DRAS-S734 CONN EDGECARD 100PS .100 R/A SLD
EMC40DTEF CONN EDGECARD 80POS .100 EYELET
AMM22DREI CONN EDGECARD 44POS .156 EYELET
相关代理商/技术参数
参数描述
MC68MH360VR25LR2 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360VR25VL 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360VR33L 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360VR33LR2 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360ZP25L 功能描述:IC MPU 32BIT QUICC 357-PBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA(25x25) 包装:托盘