参数资料
型号: MC68MH360VR25L
厂商: Freescale Semiconductor
文件页数: 110/158页
文件大小: 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
标准包装: 44
系列: M683xx
处理器类型: M683xx 32-位
速度: 25MHz
电压: 5V
安装类型: 表面贴装
封装/外壳: 357-BBGA
供应商设备封装: 357-PBGA(25x25)
包装: 托盘
Chapter 2. QMC Memory Organization
Take the example of a superchannel of several time slots:
TSn, TSn + 1, TSn + 2 ....... TSn + x
The algorithm for the receiver byte in decimal is:
(TSn + 1) * 2
The algorithm for the transmit byte in decimal is:
(TSn + x + 1) * 2
The result from these calculations is a decimal value programmed into TRNSYNC.
NOTE
Note that TSn is not necessarily the rst time slot in the frame.
For example, if a superchannel is produced from TS2, TS4, and
TS6, the message may be arranged with TS4 holding the rst
byte, then TS6, and the nal byte held in TS2 of the following
frame.
The following nine cases in Figure 2-14, named C1 to C9, show different scenarios ranging
from a single time slot per logical channel to a superchannel using several time slots. In this
application, 24 time slots are routed to this SCC from the SI RAM. After time slot 23, the
frame starts with 0 again. The arrow in all the gures illustrates the starting position.
C1 is for a single byte in TS7, so TSn = 7
Rx Byte:
(7+1) * 2 = 16
As x = 0, TSn + x = TSn = 7, so
TX Byte:
(7 + 1) * 2 = 16
C2 is a single byte in TS23, so TSn = 23. Note that time slot after 23 is 0, so in the
calculations below 23 + 1 = 0.
Rx Byte:
(23 + 1) * 2 = 0
As x = 0, TSn + x = TSn = 23, so
TX Byte:
(23 + 1) * 2 = 0
C3 is a 2-byte pattern TS7, TS8, so TSn = 7
Rx Byte:
(7 + 1) * 2 = 16
As x = 1, TSn + x = 8, so
TX Byte:
(8 + 1) * 2 = 18
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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