参数资料
型号: MC68MH360VR25L
厂商: Freescale Semiconductor
文件页数: 20/158页
文件大小: 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
标准包装: 44
系列: M683xx
处理器类型: M683xx 32-位
速度: 25MHz
电压: 5V
安装类型: 表面贴装
封装/外壳: 357-BBGA
供应商设备封装: 357-PBGA(25x25)
包装: 托盘
QMC Supplement
In the worst-case scenario, all channels open and close a buffer during the same TDM frame
resulting in the peak load all performance calculations are based on. This peak load is far
from the norm and can be controlled by the transmitter spreading the starting point of
transmit buffers over several TDM frames.
In multimaster systems, bus latency may affect the performance of the device. The
maximum external bus latency gures shown in Table 8-4 are measured from the assertion
of the BR (bus request) to the assertion of the BGACK (bus grant acknowledge); that is,
from start of bus request output being active until the cycle is completed. For multimaster
systems, bus arbitration overhead is included. Latencies of up to 40 clocks were simulated;
for values over 40, the acceptable latency may be larger.
Table 8-4 shows average maximum acceptable bus latencies, meaning the device can
tolerate longer bus delays if they are infrequent. For lengthy delays, a larger FIFO can pick
up the slack, continuing emptying or lling depending on the data ow direction.
Therefore, the larger the FIFO the more tolerant the system is to infrequent peaks in bus
delays. However, the average acceptable bus latency still depends on the overall data rate
and frame length and not on the FIFO size.
Table 8-4. Simulated Latencies
Maximum Acceptable Latency
(Bus Cycles)
Channel Combinations
25 MHz
33 MHZ
Not supported
12
SCC1: Ethernet; SCC2: 16 x 64 Kbps; SCC3: 16 x 64 Kbps
Not supported
11
SCC1: Ethernet; SCC2: 16 x 64 Kbps; SCC3: 16 x 64 Kbps;
SCC4: 64 Kbps HDLC
9 clocks
>40
SCC1: 32 x 64 Kbps. Serial bit rate 2.048 Mbps (E1/CEPT)
8 clocks
35
SCC1: 32 x 64 Kbps; SCC2: 64 Kbps; SCC3: 64 Kbps; SCC4: 64 Kbps;
all HDLC
40 clocks
>40
QMC with 24 channels. Serial bit rate 1.544 Mbps (T1)
33 clocks
>40
SCC1: 24 x 64 Kbps; SCC2: 64 Kbps; SCC3: 64 Kbps; SCC4: 64 Kbps;
all HDLC
8 clocks
24
SCC1: Ethernet; SCC2: 12 x 64 Kbps; SCC3: 12 x 64 Kbps.
TDM bit rate = 1.544 Mbps
Not supported
23
SCC1: Ethernet; SCC2: 12 x 64 Kbps; SCC3: 12 x 64 Kbps;
SCC4: 64-Kbps HDLC.
TDM bit rate = 1.544 Mbps
40 clocks
>40
SCC1: 16 x 128 Kbps. TDM bit rate = 2.048 Mbps
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相关PDF资料
PDF描述
MC68MH360CVR25L IC MPU QUICC 25MHZ 357-PBGA
HMC40DTEI CONN EDGECARD 80POS .100 EYELET
FMC50DRAS-S734 CONN EDGECARD 100PS .100 R/A SLD
EMC40DTEF CONN EDGECARD 80POS .100 EYELET
AMM22DREI CONN EDGECARD 44POS .156 EYELET
相关代理商/技术参数
参数描述
MC68MH360VR25LR2 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360VR25VL 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360VR33L 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360VR33LR2 功能描述:微处理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC68MH360ZP25L 功能描述:IC MPU 32BIT QUICC 357-PBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA(25x25) 包装:托盘