参数资料
型号: MC705JP7CPE
厂商: Freescale Semiconductor
文件页数: 106/164页
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
标准包装: 13
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 22
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.600",15.24mm)
包装: 管件
Resets
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
46
Freescale Semiconductor
The LVR reset function can be enabled or disabled by programming the LVREN bit in the MOR.
NOTE
The LVR is intended for applications where the VDD supply voltage
normally operates above 4.5 volts.
5.4.4 Illegal Address Reset
An opcode fetch (execution of an instruction) at an address that is not in the EPROM (locations
$0700–$1FFF) or the RAM (locations $0020–$00FF) generates an illegal address reset. The illegal
address reset will assert the pulldown device to pull the RESET pin low for three to four cycles of the
internal bus.
5.5 Reset States
This subsection describe how the various resets initialize the MCU.
5.5.1 CPU
A reset has these effects on the CPU:
Loads the stack pointer with $FF
Sets the I bit in the condition code register, inhibiting interrupts
Loads the program counter with the user-defined reset vector from locations $1FFE and $1FFF
Clears the stop latch, enabling the CPU clock
Clears the wait latch, bringing the CPU out of the wait mode
5.5.2 I/O Registers
A reset has these effects on input/output (I/O) registers:
Clears bits in data direction registers configuring pins as inputs:
DDRA5–DDRA0 in DDRA for port A
DDRB7–DDRB0 in DDRB for port B
DDRC7–DDRC0 in DDRC for port C(1)
Clears bits in pulldown inhibit registers to enable pulldown devices:
PDIA5–PDIA0 in PDRA for port A
PDIB7–PDIB0 in PDRB for port B
PDICH and PDICL in PDRA for port C(1)
Has no effect on port A, B, or C(1) data registers
Sets the IRQE bit in the interrupt status and control register (ISCR)
5.5.3 Core Timer
A reset has these effects on the core timer:
Clears the core timer counter register (CTCR)
Clears the core timer interrupt flag and enable bits in the core timer status and control register
(CTSCR)
Sets the real-time interrupt (RTI) rate selection bits (RT0 and RT1) such that the device will start
with the longest real-time interrupt and longest COP timeout delays
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices
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