参数资料
型号: MC705JP7CPE
厂商: Freescale Semiconductor
文件页数: 139/164页
文件大小: 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
标准包装: 13
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 22
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.600",15.24mm)
包装: 管件
Analog Subsystem
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
76
Freescale Semiconductor
Therefore, input voltages cannot be resolved if they are less than the sum
of the AVSS offset and the comparator offset, because they will always yield
a low output from the comparator.
8.3 Analog Control Register
The analog control register (ACR) controls the power-up, interrupt, and flag operation. The analog
subsystem draws current while it is operating. The resulting power consumption can be reduced
by powering down the analog subsystem when not in use (refer to 15.5 Supply Current Characteristics
(VDD = 4.5 to 5.5 Vdc)). This can be done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in
the ACR at $001D. Since these bits are cleared following a reset, the voltage comparators and the charge
current source will be powered down following a reset of the device.
The control bits in the ACR are shown in Figure 8-5. All the bits in this register are cleared by a reset of
the device.
Table 8-2. Channel Select Bus Combinations
Analog Multiplex Register
Channel Select Bus Connected to:
VREF
MUX4
MUX3
MUX2
MUX1
VDD
PB4/AN4/
TCMP
PB3/AN3/
TCAP
PB2/AN2
PB1/AN1
VSS
0
Hi-Z
On
X(1)
1. Don/t care
0
1
Hi-Z
On
Hi-Z
X(1)
0
1
0
Hi-Z
On
Hi-Z
X(1)
0
1
Hi-Z
On
Hi-Z
X(1)
0
1
0
Hi-Z
On
Hi-Z
X(1)
0
1
0
1
Hi-Z
On
Hi-Z
On
Hi-Z
X(1)
0
1
0
Hi-Z
On
Hi-Z
X(1)
0
1
Hi-Z
On
Hi-Z
X(1)
1
0
Hi-Z
On
Hi-Z
X(1)
1
0
1
Hi-Z
On
Hi-Z
On
Hi-Z
X(1)
1
0
1
0
Hi-Z
On
Hi-Z
On
Hi-Z
X(1)
1
0
1
Hi-Z
On
Hi-Z
On
Hi-Z
X(1)
1
0
Hi-Z
On
Hi-Z
X(1)
1
0
1
Hi-Z
On
Hi-Z
On
Hi-Z
X(1)
1
0
Hi-Z
On
Hi-Z
X(1)
1
Hi Z
On
Hi Z
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